TI Tiva TM4C1292NCPDT微控制器数据手册

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TI-TM4C1292NCPDT是一款高性能的Tiva系列微控制器，由德州仪器（Texas Instruments）设计和制造。该微控制器 datasheet 是关于TM4C1292NCPDT的具体规格和技术文档，包含了其详细的功能、特性以及设计者版权信息。该微控制器的核心优势在于它基于ARM Cortex-M4架构，这意味着它具备了高效的Cortex-M4内核，支持Thumb指令集，提供了出色的处理能力和低功耗性能。这使得它适用于对实时性和计算密集型任务有高要求的应用，比如物联网(IoT)设备、工业自动化、消费电子和嵌入式系统。 TM4C1292NCPDT具有丰富的外设接口，包括定时器、计数器、串行通信接口（如UART、SPI、I2C）、ADC和DMA控制器等，这些都为与外围设备的交互和数据处理提供了强大的支持。此外，它的内部闪存和RAM大小也值得一提，这有助于存储程序代码和数据，提高系统的运行效率。值得注意的是，生产数据更新至2007年至2014年，这意味着在购买或使用该产品时，应确保了解最新的规格和兼容性信息。产品的性能和功能可能会根据当时的生产标准进行测试，但可能并不包含所有参数的全面测试。用户在关键应用中使用该产品时，应仔细阅读并遵守德州仪器提供的标准保修条款和任何附加警告。文档末尾的出口通知表明，接收方同意不违反任何出口规定，这可能涉及到国际出口管理和法规要求。在使用这款微控制器时，开发者必须确保遵循相关的出口法律和政策。 TI-TM4C1292NCPDT是一款适合于高性能实时控制、数据采集和通信任务的微控制器，其优秀的硬件特性、广泛的接口以及兼容性是其核心竞争力。在选择和应用此微控制器时，务必关注其规格更新、标准保修条件以及潜在的出口限制。

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1800

Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1801

Figure 27-33. I

C Timing ....................................................................................................... 1802

Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1803

Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1803

Figure 27-36. EN0RREF_CLK 50-MHz Oscillator Characteristics ............................................ 1804

Figure 27-37. Station Management Write and Read Timing ..................................................... 1805

Figure 27-38. 100 Mb/s MII Transmit Timing ........................................................................... 1805

Figure 27-39. 100 Mb/s MII Receive Timing ............................................................................ 1806

Figure 27-40. 10 Mb/s MII Transmit Timing ............................................................................. 1806

Figure 27-41. 10 Mb/s MII Receive Timing ............................................................................. 1806

Figure 27-42. RMII Transmit Timing ....................................................................................... 1807

Figure 27-43. RMII Receive Timing ........................................................................................ 1807

Figure 27-44. ULPI Interface Timing Diagram ......................................................................... 1809

Figure A-1. Key to Part Numbers ........................................................................................ 1817

Figure A-2. TM4C1292NCPDT 128-Pin TQFP Package Diagram ......................................... 1819

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Table of Contents

List of Tables

Table 1. Revision History .................................................................................................. 44

Table 2. Documentation Conventions ................................................................................ 48

Table 1-1. TM4C1292NCPDT Microcontroller Features .......................................................... 51

Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 84

Table 2-2. Processor Register Map ....................................................................................... 85

Table 2-3. PSR Register Combinations ................................................................................. 91

Table 2-4. Memory Map ..................................................................................................... 102

Table 2-5. Memory Access Behavior ................................................................................... 106

Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 108

Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 108

Table 2-8. Exception Types ................................................................................................ 114

Table 2-9. Interrupts .......................................................................................................... 115

Table 2-10. Exception Return Behavior ................................................................................. 122

Table 2-11. Faults ............................................................................................................... 123

Table 2-12. Fault Status and Fault Address Registers ............................................................ 124

Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 126

Table 3-1. Core Peripheral Register Regions ....................................................................... 133

Table 3-2. Memory Attributes Summary .............................................................................. 137

Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 139

Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 140

Table 3-5. AP Bit Field Encoding ........................................................................................ 140

Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 141

Table 3-7. QNaN and SNaN Handling ................................................................................. 144

Table 3-8. Peripherals Register Map ................................................................................... 145

Table 3-9. Interrupt Priority Levels ...................................................................................... 170

Table 3-10. Example SIZE Field Values ................................................................................ 198

Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 207

Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 209

Table 4-3. JTAG Instruction Register Commands ................................................................. 215

Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 219

Table 5-2. Reset Sources ................................................................................................... 220

Table 5-3. Clock Source Options ........................................................................................ 230

Table 5-4. Clock Source State Following POR ..................................................................... 230

Table 5-5. System Clock Frequency ................................................................................... 235

Table 5-6. System Divisor Factors for f

vco

=480 MHz ............................................................ 237

Table 5-7. Actual PLL Frequency ........................................................................................ 237

Table 5-8. Peripheral Memory Power Control ...................................................................... 243

Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 243

Table 5-10. MOSC Configurations ........................................................................................ 246

Table 5-11. System Control Register Map ............................................................................. 247

Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 276

Table 5-13. MOSC Configurations ........................................................................................ 280

Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 299

Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 302

Table 5-16. Module Power Control ........................................................................................ 446

Table 5-17. Module Power Control ........................................................................................ 448

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™

TM4C1292NCPDT Microcontroller

Table 5-18. Module Power Control ........................................................................................ 451

Table 5-19. Module Power Control ........................................................................................ 456

Table 5-20. Module Power Control ........................................................................................ 458

Table 5-21. Module Power Control ........................................................................................ 460

Table 5-22. Module Power Control ........................................................................................ 462

Table 5-23. Module Power Control ........................................................................................ 465

Table 5-24. Module Power Control ........................................................................................ 467

Table 5-25. Module Power Control ........................................................................................ 471

Table 5-26. Module Power Control ........................................................................................ 473

Table 5-27. Module Power Control ........................................................................................ 475

Table 5-28. Module Power Control ........................................................................................ 477

Table 5-29. Module Power Control ........................................................................................ 479

Table 5-30. Module Power Control ........................................................................................ 481

Table 5-31. Module Power Control ........................................................................................ 483

Table 5-32. Module Power Control ........................................................................................ 485

Table 5-33. Module Power Control ........................................................................................ 487

Table 6-1. System Exception Register Map ......................................................................... 515

Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 526

Table 7-2. HIB Clock Source Configurations ........................................................................ 527

Table 7-3. Hibernation Module Register Map ....................................................................... 544

Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 597

Table 8-2. Flash Memory Protection Policy Combinations .................................................... 602

Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 606

Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 609

Table 8-5. Master Memory Access Availability ..................................................................... 613

Table 8-6. Flash Register Map ............................................................................................ 614

Table 9-1. μDMA Channel Assignments .............................................................................. 672

Table 9-2. Request Type Support ....................................................................................... 674

Table 9-3. Control Structure Memory Map ........................................................................... 676

Table 9-4. Channel Control Structure .................................................................................. 676

Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 685

Table 9-6. μDMA Interrupt Assignments .............................................................................. 686

Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 687

Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 688

Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 689

Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 689

Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 691

Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 691

Table 9-13. μDMA Register Map .......................................................................................... 693

Table 10-1. GPIO Pins With Special Considerations .............................................................. 735

Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 735

Table 10-3. GPIO Drive Strength Options .............................................................................. 746

Table 10-4. GPIO Pad Configuration Examples ..................................................................... 747

Table 10-5. GPIO Interrupt Configuration Example ................................................................ 748

Table 10-6. GPIO Pins With Special Considerations .............................................................. 749

Table 10-7. GPIO Register Map ........................................................................................... 750

Table 10-8. GPIO Pins With Special Considerations .............................................................. 763

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Table 10-9. GPIO Pins With Special Considerations .............................................................. 769

Table 10-10. GPIO Pins With Special Considerations .............................................................. 771

Table 10-11. GPIO Pins With Special Considerations .............................................................. 774

Table 10-12. GPIO Pins With Special Considerations .............................................................. 780

Table 10-13. GPIO Drive Strength Options .............................................................................. 793

Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 810

Table 11-2. EPI Interface Options ......................................................................................... 815

Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 816

Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 820

Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 821

Table 11-6. Chip Select Configuration Register Assignment ................................................... 822

Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 822

Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 824

Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 826

Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 831

Table 11-11. Data Phase Wait State Programming .................................................................. 836

Table 11-12. EPI General-Purpose Signal Connections ........................................................... 842

Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 847

Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 873

Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 879

Table 12-1. Endian Configuration ......................................................................................... 940

Table 12-2. Endian Configuration with Bit Reversal ................................................................ 940

Table 12-3. CCM Register Map ............................................................................................ 942

Table 13-1. Available CCP Pins ............................................................................................ 949

Table 13-2. General-Purpose Timers Signals (128TQFP) ....................................................... 950

Table 13-3. General-Purpose Timer Capabilities .................................................................... 951

Table 13-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 953

Table 13-5. 16-Bit Timer With Prescaler Configurations ......................................................... 954

Table 13-6. Counter Values When the Timer is Enabled in RTC Mode .................................... 955

Table 13-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 956

Table 13-8. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 957

Table 13-9. Counter Values When the Timer is Enabled in PWM Mode ................................... 959

Table 13-10. Timeout Actions for GPTM Modes ...................................................................... 962

Table 13-11. Timers Register Map .......................................................................................... 967

Table 14-1. Watchdog Timers Register Map ........................................................................ 1024

Table 15-1. ADC Signals (128TQFP) .................................................................................. 1048

Table 15-2. Samples and FIFO Depth of Sequencers .......................................................... 1049

Table 15-3. Sample and Hold Width in ADC Clocks ............................................................. 1051

Table 15-4. R

and F

CONV

Values with Varying N

Values and F

ADC

= 16 MHz ..................... 1052

Table 15-5. R

and F

CONV

Values with Varying N

Values and F

ADC

= 32 MHz ..................... 1052

Table 15-6. Differential Sampling Pairs ............................................................................... 1059

Table 15-7. ADC Register Map ........................................................................................... 1066

Table 15-8. Sample and Hold Width in ADC Clocks ............................................................. 1120

Table 15-9. Sample and Hold Width in ADC Clocks ............................................................. 1132

Table 15-10. Sample and Hold Width in ADC Clocks ............................................................. 1140

Table 16-1. UART Signals (128TQFP) ................................................................................ 1156

Table 16-2. Flow Control Mode ........................................................................................... 1162

Table 16-3. UART Register Map ......................................................................................... 1166

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TM4C1292NCPDT Microcontroller

Table 17-1. SSI Signals (128TQFP) .................................................................................... 1221

Table 17-2. QSSI Transaction Encodings ............................................................................ 1224

Table 17-3. SSInFss Functionality ...................................................................................... 1225

Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1227

Table 17-5. SSI Register Map ............................................................................................. 1236

Table 18-1. I2C Signals (128TQFP) .................................................................................... 1270

Table 18-2. Examples of I

C Master Timer Period Versus Speed Mode ................................. 1277

Table 18-3. Examples of I

C Master Timer Period in High-Speed Mode ................................ 1278

Table 18-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1293

Table 18-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1301

Table 19-1. Controller Area Network Signals (128TQFP) ...................................................... 1350

Table 19-2. Message Object Configurations ........................................................................ 1356

Table 19-3. CAN Protocol Ranges ...................................................................................... 1364

Table 19-4. CANBIT Register Values .................................................................................. 1364

Table 19-5. CAN Register Map ........................................................................................... 1368

Table 20-1. Ethernet Signals (128TQFP) ............................................................................. 1401

Table 20-2. MII and RMII Interface Signals .......................................................................... 1404

Table 20-3. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1409

Table 20-4. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1412

Table 20-5. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1413

Table 20-6. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1413

Table 20-7. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1413

Table 20-8. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1413

Table 20-9. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1414

Table 20-10. RDES0 Checksum Offload bits ......................................................................... 1416

Table 20-11. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1417

Table 20-12. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1417

Table 20-13. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1417

Table 20-14. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1418

Table 20-15. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1419

Table 20-16. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1419

Table 20-17. TX MAC Flow Control ...................................................................................... 1432

Table 20-18. RX MAC Flow Control ...................................................................................... 1432

Table 20-19. VLAN Match Status .......................................................................................... 1445

Table 20-20. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1447

Table 20-21. Ethernet Register Map ..................................................................................... 1454

Table 20-22. PPSCTRL Bit Field Values ............................................................................... 1535

Table 21-1. USB Signals (128TQFP) .................................................................................. 1575

Table 21-2. List of Registers ............................................................................................... 1576

Table 22-1. Analog Comparators Signals (128TQFP) ........................................................... 1583

Table 22-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1585

Table 22-3. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1586

Table 22-4. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1587

Table 22-5. Analog Comparators Register Map ................................................................... 1588

Table 23-1. PWM Signals (128TQFP) ................................................................................. 1601

Table 23-2. PWM Register Map .......................................................................................... 1608

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