R-CarM3硬件用户手册：V0.10，2020年12月，汽车信息终端应用SoC概览

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R-CarM3 使用手册是针对汽车行业专用系统-on-chip (Soc) 的一份详细文档，专为R-CarH3/M3 Starter Kit设计。该手册版本为Rev.0.10，发布于2020年12月，属于Renesas Electronics Corp. 的R-Car家族和R-Car Gen3系列的初步资料。这份文档的主要内容涵盖了硬件信息，旨在展示R-CarM3芯片在汽车信息终端应用中的操作原理和功能特性。手册首先强调了所有提供的信息仅代表产品在出版时的状态，并可能随时根据Renesas Electronics Corp. 的通知进行更新。用户应通过Renesas官方网站（http://www.renesas.com）等途径获取最新发布的资料，确保设计的准确性。手册中的电路描述、软件示例以及相关的技术信息主要用于指导半导体产品的操作演示和应用案例，但使用者需自行承担在产品或系统设计中整合这些电路、软件和信息的责任。Renesas Electronics明确声明，对因使用这些信息而导致的任何损失或损害，公司不承担任何责任，包括但不限于第三方可能产生的损失。对于开发人员来说，这份文档提供了关键的硬件接口指南、功能规格、功耗数据以及安全特性的详细介绍，以便他们能够有效利用R-CarM3芯片来构建高性能、安全的汽车电子系统。用户在实际应用中应结合实际项目需求，仔细阅读并理解手册中的警告和注意事项，以确保系统的稳定性和可靠性。在使用过程中，开发者需要遵守版权声明，尊重Renesas Electronics Corporation 的所有权益。同时，考虑到汽车行业的严格标准和法规，用户还需要确保遵循相关的安全标准和电磁兼容性规定。 R-CarM3 使用手册为从事汽车电子系统设计的专业人士提供了一手的技术支持，帮助他们在开发过程中充分利用Renesas的先进技术，实现高效、安全的汽车信息系统。

50.2.13 Unread frame counter stop level register (UFCS) ................................................................................... 50-36

50.2.14 Unread Frame Counter Register i (UFCVi) (i = 0 to 4) .......................................................................... 50-37

50.2.15 Unread Frame Counter Decrement Register i (UFCDi) (i = 0 to 4) ........................................................ 50-39

50.2.16 Separation Filter Offset Register (SFO) .................................................................................................. 50-40

50.2.17 Separation Filter Pattern Register i (SFPi) (i = 0 to 31) .......................................................................... 50-41

50.2.18 Separation Filter Value register i (SFVi) (i = 0 to 1) ............................................................................... 50-42

50.2.19 Separation Filter Mask Register i (SFMi) (i = 0 or 1) ............................................................................. 50-43

50.2.20 Separation Filter Load register (SFL) ...................................................................................................... 50-44

50.2.22 Current Incremental Address Register r (CIARr) (r = 0 to 17) ............................................................... 50-45

50.2.23 Last Incremental Address Register r (LIARr) (r = 0 to 17) ..................................................................... 50-46

50.2.24 Transmit Configuration Register (TGC) ................................................................................................. 50-47

50.2.25 Transmit Configuration Control Register (TCCR) .................................................................................. 50-49

50.2.26 Transmit Status Register (TSR) .............................................................................................................. 50-52

50.2.27 E-MAC status FIFO Access register (MFA) ........................................................................................... 50-55

50.2.28 Time Stamp FIFO Access Register 0 (TFA0) ......................................................................................... 50-57

50.2.29 Time Stamp FIFO Access Register 1 (TFA1) ......................................................................................... 50-58

50.2.30 Time Stamp FIFO Access Register 2 (TFA2) ......................................................................................... 50-59

50.2.31 Version and Release Register (VRR) ...................................................................................................... 50-60

50.2.32 CBS Increment Value Register c (CIVRc) (c = 0 or 1) ........................................................................... 50-61

50.2.33 CBS Decrement Value Register c (CDVRc) (c = 0 or 1) ........................................................................ 50-62

50.2.34 CBS Upper Limit Register c (CULc) (c = 0 or 1) ................................................................................... 50-63

50.2.35 CBS Lower Limit Register c (CLLc) (c = 0 or 1) ................................................................................... 50-64

50.2.36 Descriptor Interrupt Control Register (DIC) ........................................................................................... 50-65

50.2.37 Descriptor Interrupt Status Register (DIS) .............................................................................................. 50-67

50.2.38 Error Interrupt Control Register (EIC) .................................................................................................... 50-69

50.2.39 Error Interrupt Status Register (EIS) ....................................................................................................... 50-72

50.2.40 Receive Interrupt Control Register 0 (RIC0) .......................................................................................... 50-77

50.2.41 Receive Interrupt Status Register 0 (RIS0) ............................................................................................. 50-79

50.2.42 Receive Interrupt Control Register 1 (RIC1) .......................................................................................... 50-81

50.2.43 Receive Interrupt Status Register 1 (RIS1) ............................................................................................. 50-85

50.2.44 Receive Interrupt Control Register 2 (RIC2) .......................................................................................... 50-92

50.2.45 Receive Interrupt Status Register 2 (RIS2) ............................................................................................. 50-96

50.2.46 Transmit Interrupt Control Register (TIC) .............................................................................................. 50-99

50.2.47 Transmit Interrupt Status Register (TIS) ............................................................................................... 50-102

50.2.48 Interrupt Summary Status Register (ISS) .............................................................................................. 50-107

50.2.49 Common Interrupt Enable register (CIE) .............................................................................................. 50-111

50.2.50 Reception Interrupt Control register 3 (RIC3) ...................................................................................... 50-113

50.2.51 Reception Interrupt Status register 3 (RIS3) ......................................................................................... 50-117

50.2.52 gPTP Configuration Control Register (GCCR) ..................................................................................... 50-122

50.2.53 gPTP Maximum Transit Time Configuration Register (GMTT) .......................................................... 50-125

50.2.54 gPTP Presentation Time Comparison Register (GPTC) ....................................................................... 50-126

50.2.55 gPTP Timer Increment Configuration Register (GTI) .......................................................................... 50-127

50.2.56 gPTP timer offset register i (GTOi) (i = 0 to 2) ..................................................................................... 50-128

50.2.57 gPTP Interrupt Control Register (GIC) ................................................................................................. 50-129

50.2.58 gPTP interrupt status register (GIS) ...................................................................................................... 50-134

50.2.59 gPTP Captured Presentation Time register (GCPT) .............................................................................. 50-141

50.2.60 gPTP Timer Capture Register i (GCTi) (i = 0 to 2) ............................................................................... 50-142

50.2.61 gPTP Status Register (GSR) .................................................................................................................. 50-143

50.2.62 gPTP Interrupt Enable register (GIE) .................................................................................................... 50-148

50.2.63 gPTP Interrupt Disable register (GID) .................................................................................................. 50-152

50.2.64 gPTP Interrupt Line selection register (GIL) ........................................................................................ 50-156

50.2.65 gPTP Avtp Capture Prescaler register (GACP) ..................................................................................... 50-160

50.2.66 gPTP Presentation Time FIFO register i (GPTFi) (i = 0 to 3) ............................................................... 50-161

50.2.67 gPTP Captured Avtp Time register i (GCATi) (i = 0 to 15) ................................................................. 50-162

50.2.68 Descriptor Interrupt Line selection register (DIL)................................................................................. 50-163

50.2.69 Error Interrupt Line selection register (EIL) ......................................................................................... 50-165

50.2.70 Transmission Interrupt Line selection register (TIL) ............................................................................ 50-167

50.2.71 Descriptor Interrupt Enable register (DIE) ............................................................................................ 50-168

50.2.72 Descriptor Interrupt Disable register (DID) .......................................................................................... 50-171

50.2.73 Error Interrupt Enable register (EIE) ..................................................................................................... 50-174

50.2.74 Error Interrupt Disable register (EID) ................................................................................................... 50-176

50.2.75 Reception Interrupt Enable register 0 (RIE0) ........................................................................................ 50-178

50.2.76 Reception Interrupt Disable register 0 (RID0) ...................................................................................... 50-181

50.2.77 Reception Interrupt Enable register 1 (RIE1) ........................................................................................ 50-184

50.2.78 Reception Interrupt Disable register 1 (RID1) ...................................................................................... 50-187

50.2.79 Reception Interrupt Enable register 2 (RIE2) ........................................................................................ 50-190

50.2.80 Reception Interrupt Disable register 2 (RID2) ...................................................................................... 50-193

50.2.81 Transmission Interrupt Enable register (TIE) ........................................................................................ 50-196

50.2.82 Transmission Interrupt Disable register (TID) ...................................................................................... 50-198

50.2.83 Reception Interrupt Enable register 3 (RIE3) ........................................................................................ 50-200

50.2.84 Reception Interrupt Disable register 3 (RID3) ...................................................................................... 50-203

50.2.85 E-MAC Mode Register (ECMR) .......................................................................................................... 50-206

50.2.86 Receive Frame Length Register (RFLR) ............................................................................................... 50-209

50.2.87 E-MAC Status Register (ECSR) ........................................................................................................... 50-210

50.2.88 E-MAC Interrupt Permission Register (ECSIPR) ................................................................................. 50-212

50.2.89 PHY Interface Register (PIR) ................................................................................................................ 50-213

50.2.90 PHY Status Register (PSR) ................................................................................................................... 50-214

50.2.91 PHY_INT Polarity Register (PIPR) ...................................................................................................... 50-215

50.2.92 Automatic PAUSE frame register (APR) .............................................................................................. 50-216

50.2.93 Manual PAUSE Frame Register (MPR) ................................................................................................ 50-217

50.2.94 PAUSE Frame Transmit Counter (PFTCR) .......................................................................................... 50-218

50.2.95 PAUSE Frame Receive Counter (PFRCR) ........................................................................................... 50-219

50.2.96 Automatic PAUSE frame retransmit count register (TPAUSER) ......................................................... 50-220

50.2.97 PAUSE frame transmit times counter (PFTTCR) ................................................................................. 50-221

50.2.98 E-MAC Mode Register 2 (GECMR) ..................................................................................................... 50-222

50.2.99 E-MAC Address High Register (MAHR) ............................................................................................. 50-223

50.2.100 E-MAC Address Low Register (MALR) .............................................................................................. 50-224

50.2.101 Transmit retry over counter register (TROCR) ..................................................................................... 50-225

50.2.102 CRC Error Frame Receive Counter Register (CEFCR) ........................................................................ 50-226

50.2.103 Frame Receive Error Counter Register (FRECR) ................................................................................. 50-227

50.2.104 Too-Short Frame Receive Counter Register (TSFRCR) ....................................................................... 50-228

50.2.105 Too-Long Frame Receive Counter Register (TLFRCR) ....................................................................... 50-229

50.2.106 Residual-Bit Frame Receive Counter Register (RFCR) ........................................................................ 50-230

50.2.107 Multicast Address Frame Receive Counter Register (MAFCR) ........................................................... 50-231

50.3 Operation ......................................................................................................................................................... 50-232

50.3.1 AVB-DMAC Operating Modes ............................................................................................................ 50-233

50.3.2 Common Control for Transmission and Reception ............................................................................... 50-237

50.3.3 Descriptors ............................................................................................................................................ 50-245

50.3.4 Control in Reception ............................................................................................................................. 50-257

50.3.5 Transmission Control ............................................................................................................................ 50-272

50.3.6 CBS (Credit-Based Shaping) ................................................................................................................. 50-287

50.3.7 Time Synchronization ........................................................................................................................... 50-293

50.3.8 Support for IEEE 1722 .......................................................................................................................... 50-296

50.3.9 Flow Control ......................................................................................................................................... 50-306

50.3.10 Magic Packet Detection......................................................................................................................... 50-307

50.3.11 Interrupts ............................................................................................................................................... 50-308

50.3.12 Flows of Operations .............................................................................................................................. 50-314

50.3.13 Connection to PHY-LSI ........................................................................................................................ 50-327

50.3.14 Usage Notes .......................................................................................................................................... 50-332

50.4 Usage Notes ..................................................................................................................................................... 50-333

50.4.1 Checksum Calculation of Ethernet Frames ........................................................................................... 50-333

50.4.2 Data Transfer Function Stops after Read Access Error ......................................................................... 50-334

50.4.3 Power Down Request ............................................................................................................................ 50-335

52A. CAN-FD ............................................................................................................................. 52A-1

52A.1 Overview ........................................................................................................................................................... 52A-1

52A.1.1 Functional Overview .............................................................................................................................. 52A-1

52A.1.2 Interface Mode ....................................................................................................................................... 52A-3

52A.2 Block Diagram .................................................................................................................................................. 52A-4

52A.3 External Pins ..................................................................................................................................................... 52A-5

52A.4 Connected module ............................................................................................................................................ 52A-5

52A.5 Features of RS-CANFD .................................................................................................................................... 52A-6

52A.5.1 Register Base Address ............................................................................................................................ 52A-6

52A.6 Registers Configuration (classical CAN mode) ................................................................................................ 52A-7

52A.6.1 List of Registers ..................................................................................................................................... 52A-7

52A.7 Register Description (classical CAN mode) ................................................................................................... 52A-12

52A.7.1 Details of Interface Mode Related Registers ........................................................................................ 52A-12

52A.7.1.1 RSCFDnCFDGRMCFG - Global Interface Mode Select Register ......................................... 52A-12

52A.7.2 Details of Channel Related Registers ................................................................................................... 52A-13

52A.7.2.1 RSCFDnCmCFG — Channel Configuration Register (m = 0, 1) ........................................... 52A-13

52A.7.2.2 RSCFDnCmCTR — Channel Control Register (m = 0 or 1) .................................................. 52A-15

52A.7.2.3 RSCFDnCmSTS — Channel Status Register (m = 0 or 1) ..................................................... 52A-20

52A.7.2.4 RSCFDnCmERFL — Channel Error Flag Register (m = 0 or 1) ........................................... 52A-22

52A.7.3 Details of Global Related Registers ..................................................................................................... 52A-26

52A.7.3.1 RSCFDnGCFG - Global Configuration Register .................................................................... 52A-26

52A.7.3.2 RSCFDnGCTR — Global Control Register ........................................................................... 52A-29

52A.7.3.3 RSCFDnGSTS — Global Status Register ............................................................................... 52A-31

52A.7.3.4 RSCFDnGERFL — Global Error Flag Register ..................................................................... 52A-33

52A.7.3.5 RSCFDnGTSC — Global Timestamp Counter Register ........................................................ 52A-35

52A.7.3.6 RSCFDnGTINTSTS0 — Global TX Interrupt Status Register 0 ........................................... 52A-36

52A.7.3.7 RSCFDnGTINTSTS1 — Global TX Interrupt Status Register 1 ........................................... 52A-39

52A.7.4 Details of Receive Rule Related Registers ........................................................................................... 52A-40

52A.7.4.1 RSCFDnGAFLECTR — Receive Rule Entry Control Register ............................................. 52A-40

52A.7.4.2 RSCFDnGAFLCFG0 — Receive Rule Configuration Register 0 .......................................... 52A-41

52A.7.4.3 RSCFDnGAFLCFG1 — Receive Rule Configuration Register 1 .......................................... 52A-42

52A.7.4.4 RSCFDnGAFLIDj — Receive Rule ID Register (j = 0 to 15) ................................................ 52A-43

52A.7.4.5 RSCFDnGAFLMj — Receive Rule Mask Register (j = 0 to 15) ............................................ 52A-45

52A.7.4.6 RSCFDnGAFLP0_j — Receive Rule Pointer 0 Register (j = 0 to 15) ................................... 52A-46

52A.7.4.7 RSCFDnGAFLP1_j — Receive Rule Pointer 1 Register (j = 0 to 15) ................................... 52A-48

52A.7.5 Details of Receive Buffer Related Registers ........................................................................................ 52A-49

52A.7.5.1 RSCFDnRMNB - Receive Buffer Number Register ............................................................... 52A-49

52A.7.5.2 RSCFDnRMNDy — Receive Buffer New Data Register (y = 0) ........................................... 52A-50

52A.7.5.3 RSCFDnRMIDq — Receive Buffer ID Register (q = 0 to 31) ............................................... 52A-51

52A.7.5.4 RSCFDnRMPTRq — Receive Buffer Pointer Register (q = 0 to 31) ..................................... 52A-52

52A.7.5.5 RSCFDnRMDF0_q — Receive Buffer Data Field 0 Register (q = 0 to 31) ........................... 52A-53

52A.7.5.6 RSCFDnRMDF1_q — Receive Buffer Data Field 1 Register (q = 0 to 31) ........................... 52A-54

52A.7.6 Details of Receive FIFO Buffer Related Registers............................................................................... 52A-55

52A.7.6.1 RSCFDnRFCCx — Receive FIFO Buffer Configuration and Control Register

(x = 0 to 7) ............................................................................................................................... 52A-55

52A.7.6.2 RSCFDnRFSTSx — Receive FIFO Buffer Status Register (x = 0 to 7) ................................. 52A-57

52A.7.6.3 RSCFDnRFPCTRx — Receive FIFO Buffer Pointer Control Register (x = 0 to 7) ............... 52A-59

52A.7.6.4 RSCFDnRFIDx — Receive FIFO Buffer Access ID Register (x = 0 to 7) ............................. 52A-60

52A.7.6.5 RSCFDnRFPTRx — Receive FIFO Buffer Access Pointer Register (x = 0 to 7) .................. 52A-61

52A.7.6.6 RSCFDnRFDF0_x — Receive FIFO Buffer Access Data Field 0 Register (x = 0 to 7) ........ 52A-62

52A.7.6.7 RSCFDnRFDF1_x — Receive FIFO Buffer Access Data Field 1 Register (x = 0 to 7) ........ 52A-63

52A.7.7 Details of Transmit/Receive FIFO Buffer Related Registers ............................................................... 52A-64

52A.7.7.1 RSCFDnCFCCk — Transmit/receive FIFO Buffer Configuration and Control Register k

(k = 0 to 5) ............................................................................................................................... 52A-64

52A.7.7.2 RSCFDnCFSTSk — Transmit/receive FIFO Buffer Status Register (k = 0 to 5) ................... 52A-68

52A.7.7.3 RSCFDnCFPCTRk — Transmit/receive FIFO Buffer Pointer Control Register

(k = 0 to 5) ............................................................................................................................... 52A-72

52A.7.7.4 RSCFDnCFIDk — Transmit/receive FIFO Buffer Access ID Register (k = 0 to 5) ............... 52A-74

52A.7.7.5 RSCFDnCFPTRk — Transmit/receive FIFO Buffer Access Pointer Register (k = 0 to 5) .... 52A-76

52A.7.7.6 RSCFDnCFDF0_k — Transmit/receive FIFO Buffer Access Data Field 0 Register

(k = 0 to 5) ............................................................................................................................... 52A-78

52A.7.7.7 RSCFDnCFDF1_k — Transmit/receive FIFO Buffer Access Data Field 1 Register

(k = 0 to 5) ............................................................................................................................... 52A-79

52A.7.8 Details of FIFO Status Related Registers ............................................................................................. 52A-80

52A.7.8.1 RSCFDnFESTS — FIFO Empty Status Register ................................................................... 52A-80

52A.7.8.2 RSCFDnFFSTS — FIFO Full Status Register ........................................................................ 52A-82

52A.7.8.3 RSCFDnFMSTS — FIFO Message Lost Status Register ....................................................... 52A-84

52A.7.8.4 RSCFDnRFISTS — Receive FIFO Buffer Interrupt Flag Status Register ............................. 52A-86

52A.7.8.5 RSCFDnCFRISTS — Transmit/receive FIFO Buffer Receive Interrupt Flag

Status Register ......................................................................................................................... 52A-87

52A.7.8.6 RSCFDnCFTISTS — Transmit/receive FIFO Buffer Transmit Interrupt Flag

Status Register ......................................................................................................................... 52A-88

52A.7.9 Details of Transmit Buffer Related Registers ....................................................................................... 52A-89

52A.7.9.1 RSCFDnTMCp — Transmit Buffer Control Register (p = 0 to 31)........................................ 52A-89

52A.7.9.2 RSCFDnTMSTSp — Transmit Buffer Status Register (p = 0 to 31) ...................................... 52A-91

52A.7.9.3 RSCFDnTMIDp — Transmit Buffer ID Register (p = 0 to 31) .............................................. 52A-92

52A.7.9.4 RSCFDnTMPTRp — Transmit Buffer Pointer Register (p = 0 to 31) .................................... 52A-94

52A.7.9.5 RSCFDnTMDF0_p — Transmit Buffer Data Field 0 Register (p = 0 to 31) .......................... 52A-96

52A.7.9.6 RSCFDnTMDF1_p — Transmit Buffer Data Field 1 Register (p = 0 to 31) .......................... 52A-97

52A.7.9.7 RSCFDnTMIECy — Transmit Buffer Interrupt Enable Configuration Register (y = 0) ........ 52A-98

52A.7.10 Details of Transmit Buffer Status Related Registers .......................................................................... 52A-100

52A.7.10.1 RSCFDnTMTRSTSy — Transmit Buffer Transmit Request Status Register (y = 0) ........... 52A-100

52A.7.10.2 RSCFDnTMTARSTSy — Transmit Buffer Transmit Abort Request Status Register

(y = 0) .................................................................................................................................... 52A-102

52A.7.10.3 RSCFDnTMTCSTSy — Transmit Buffer Transmit Complete Status Register (y = 0) ........ 52A-104

52A.7.10.4 RSCFDnTMTASTSy — Transmit Buffer Transmit Abort Status Register (y = 0) .............. 52A-106

52A.7.11 Details of Transmit Queue Related Registers ..................................................................................... 52A-108

52A.7.11.1 RSCFDnTXQCCm — Transmit Queue Configuration and Control Register

(m = 0 or 1) ........................................................................................................................... 52A-108

52A.7.11.2 RSCFDnTXQSTSm — Transmit Queue Status Register (m = 0 or 1) ................................. 52A-110

52A.7.11.3 RSCFDnTXQPCTRm — Transmit Queue Pointer Control Register (m = 0 or 1) ............... 52A-112

52A.7.12 Details of Transmit History Related Registers ................................................................................... 52A-113

52A.7.12.1 RSCFDnTHLCCm — Transmit History Configuration and Control Register

(m = 0 or 1) ........................................................................................................................... 52A-113

52A.7.12.2 RSCFDnTHLSTSm — Transmit History Status Register (m = 0 or 1) ................................ 52A-115

52A.7.12.3 RSCFDnTHLPCTRm — Transmit History Pointer Control Register (m = 0 or 1) .............. 52A-117

52A.7.12.4 RSCFDnTHLACCm — Transmit History Access Register (m = 0 or 1) ............................. 52A-118

52A.7.13 Details of Test Related Registers ....................................................................................................... 52A-119

52A.7.13.1 RSCFDnGTSTCFG — Global Test Configuration Register ................................................ 52A-119

52A.7.13.2 RSCFDnGTSTCTR — Global Test Control Register .......................................................... 52A-120

52A.7.13.3 RSCFDnGLOCKK — Global Lock Key Register ................................................................ 52A-121

52A.7.13.4 RSCFDnRPGACCr — RAM Test Page Access Register (r = 0 to 63) ................................. 52A-122

52A.8 Registers Configuration (CAN FD mode) .................................................................................................... 52A-123

52A.8.1 List of Registers ................................................................................................................................. 52A-123

52A.9 Register Description (CAN FD mode) .......................................................................................................... 52A-129

52A.9.1 Details of Interface Mode Related Registers ...................................................................................... 52A-129

52A.9.1.1 RSCFDnCFDGRMCFG — Global Interface Mode Select Register .................................... 52A-129

52A.9.2 Details of Channel Related Registers ................................................................................................. 52A-130

52A.9.2.1 RSCFDnCFDCmNCFG — Channel Normal Bit Rate Configuration Register

(m = 0 or 1) ........................................................................................................................... 52A-130

52A.9.2.2 RSCFDnCFDCmCTR — Channel Control Register (m = 0 or 1) ........................................ 52A-132

52A.9.2.3 RSCFDnCFDCmSTS — Channel Status Register (m = 0 or 1) ........................................... 52A-137

52A.9.2.4 RSCFDnCFDCmERFL — Channel Error Flag Status Register (m = 0 or 1) ....................... 52A-140

52A.9.2.5 RSCFDnCFDCmDCFG — Channel Data Bit Rate Configuration Register (m = 0 or 1) .... 52A-144

52A.9.2.6 RSCFDnCFDCmFDCFG — Channel CAN FD Configuration Register (m = 0 or 1) ......... 52A-146

52A.9.2.7 RSCFDnCFDCmFDCTR — Channel CAN FD Control Register (m = 0 or 1) .................... 52A-150

52A.9.2.8 RSCFDnCFDCmFDSTS — Channel CAN FD Status Register (m = 0 or 1) ....................... 52A-151

52A.9.2.9 RSCFDnCFDCmFDCRC — Channel CAN FD CRC Register (m = 0 or 1) ....................... 52A-153

52A.9.3 Details of Global Related Registers ................................................................................................... 52A-154

52A.9.3.1 RSCFDnCFDGCFG — Global Configuration Register ....................................................... 52A-154

52A.9.3.2 RSCFDnCFDGCTR — Global Control Register .................................................................. 52A-157

52A.9.3.3 RSCFDnCFDGSTS — Global Status Register ..................................................................... 52A-159

52A.9.3.4 RSCFDnCFDGERFL — Global Error Flag Register ........................................................... 52A-161

52A.9.3.5 RSCFDnCFDGTSC — Global Timestamp Counter Register .............................................. 52A-163

52A.9.3.6 RSCFDnCFDGTINTSTS0 — Global TX Interrupt Status Register 0 .................................. 52A-164

52A.9.3.7 RSCFDnCFDGTINTSTS1 — Global TX Interrupt Status Register 1 .................................. 52A-167

52A.9.4 Details of Receive Rule Related Registers ......................................................................................... 52A-168

52A.9.4.1 RSCFDnCFDGAFLECTR — Receive Rule Entry Control Register ................................... 52A-168

52A.9.4.2 RSCFDnCFDGAFLCFG0 — Receive Rule Configuration Register 0 ................................ 52A-169

52A.9.4.3 RSCFDnCFDGAFLCFG1 — Receive Rule Configuration Register 1 ................................ 52A-170

52A.9.4.4 RSCFDnCFDGAFLIDj — Receive Rule ID Register (j = 0 to 15) ...................................... 52A-171

52A.9.4.5 RSCFDnCFDGAFLMj — Receive Rule Mask Register (j = 0 to 15) .................................. 52A-173

52A.9.4.6 RSCFDnCFDGAFLP0_j — Receive Rule Pointer 0 Register (j = 0 to 15) .......................... 52A-174

52A.9.4.7 RSCFDnCFDGAFLP1_j — Receive Rule Pointer 1 Register (j = 0 to 15) .......................... 52A-176

52A.9.5 Details of Receive Buffer Related Registers ...................................................................................... 52A-177

52A.9.5.1 RSCFDnCFDRMNB — Receive Buffer Number Register .................................................. 52A-177

52A.9.5.2 RSCFDnCFDRMNDy — Receive Buffer New Data Register (y = 0) ................................. 52A-178

52A.9.5.3 RSCFDnCFDRMIDq — Receive Buffer ID Register (q = 0 to 31)...................................... 52A-179

52A.9.5.4 RSCFDnCFDRMPTRq — Receive Buffer Pointer Register (q = 0 to 31) ........................... 52A-180

52A.9.5.5 RSCFDnCFDRMFDSTSq — Receive Buffer CAN FD Status Register (q = 0 to 31) ......... 52A-182

52A.9.5.6 RSCFDnCFDRMDFb_q — Receive Buffer Data Field b Register

(b = 0 to 4, q = 0 to 31) ......................................................................................................... 52A-183

52A.9.6 Details of Receive FIFO Buffer Related Registers............................................................................. 52A-184

52A.9.6.1 RSCFDnCFDRFCCx — Receive FIFO Buffer Configuration and Control Register

(x = 0 to 7) ............................................................................................................................. 52A-184

52A.9.6.2 RSCFDnCFDRFSTSx — Receive FIFO Buffer Status Register (x = 0 to 7) ....................... 52A-187

52A.9.6.3 RSCFDnCFDRFPCTRx — Receive FIFO Buffer Pointer Control Register (x = 0 to 7) ..... 52A-189

52A.9.6.4 RSCFDnCFDRFIDx — Receive FIFO Buffer Access ID Register (x = 0 to 7) ................... 52A-190

52A.9.6.5 RSCFDnCFDRFPTRx — Receive FIFO Buffer Access Pointer Register (x = 0 to 7) ......... 52A-192

52A.9.6.6 RSCFDnCFDRFFDSTSx — Receive FIFO CAN FD Status Register (x = 0 to 7) .............. 52A-194

52A.9.6.7 RSCFDnCFDRFDFd_x — Receive FIFO Buffer Access Data Field d Register

(d = 0 to 15, x = 0 to 7) ......................................................................................................... 52A-195

52A.9.7 Details of Transmit/Receive FIFO Buffer Related Registers ............................................................. 52A-196

52A.9.7.1 RSCFDnCFDCFCCk — Transmit/receive FIFO Buffer Configuration and Control Register k

(k = 0 to 5) ............................................................................................................................. 52A-196

52A.9.7.2 RSCFDnCFDCFSTSk — Transmit/receive FIFO Buffer Status Register (k = 0 to 5) ......... 52A-201

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