Analog Devices的Blackfin DSP处理器详解

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"Blackfin DSP处理器，ADSP-BF504/ADSP-BF504F/ADSP-BF506F数据表" Blackfin DSP（Digital Signal Processor）是由Analog Devices公司开发的一种高性能嵌入式处理器，旨在处理数字信号处理任务。Blackfin系列处理器以其独特的架构融合了DSP和微控制器的功能，使其在音频、视频、图像处理以及通信等领域有着广泛的应用。标题提及的ADSP-BF504、ADSP-BF504F和ADSP-BF506F是Blackfin家族中的特定型号，它们在Rev.A版本的数据表中进行了详细描述。这些处理器具有以下关键特性： 1. **高性能Blackfin处理器**：这三款处理器的时钟频率高达400MHz，提供高速计算能力，适用于实时处理复杂算法。 2. **强大的硬件加速器**：每个Blackfin处理器配备了两个16位乘累加单元(MACs)、两个40位算术逻辑单元(ALUs)以及四个8位视频ALUs，这样的配置使得它们在处理多媒体和信号处理任务时效率极高。 3. **40位移位器**：40位的移位器允许进行大范围的数据操作，提高了数据处理的灵活性和精度。 4. **RISC-like架构**：Blackfin处理器采用类似于精简指令集计算机(RISC)的架构，简化了编程，并有利于编译器优化，从而提升软件开发效率。 5. **高级调试和性能监控**：集成的调试、追踪和性能监测功能为开发者提供了强大的工具，帮助他们优化代码，找出潜在问题。 6. **电源电压适应性**：这些处理器可以接受不同范围的供电电压，适应不同的内部和I/O操作需求，增强了系统设计的灵活性。 7. **知识产权保护**：文件指出，Blackfin商标和Blackfin徽标是Analog Devices公司的注册商标，强调了其知识产权的重要性。尽管数据表中并未详细列出所有规格和功能，但可以推断，Blackfin DSP处理器提供了全面的外设接口、内存管理单元以及高效的能源管理，使其成为各种嵌入式应用的理想选择。在实际应用中，这些处理器常用于视频编码/解码、语音处理、图像分析、网络协议处理等场景。用户在使用时应遵守Analog Devices提供的规格和条款，同时注意可能涉及的专利侵权风险。Analog Devices公司不对其使用承担责任，也不默示提供任何专利许可。如需了解更多详细信息，可以访问Analog Devices的官方网站获取完整数据表和技术支持。

Rev. A | Page 13 of 80 | July 2011

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

Each mailbox consists of eight 16-bit data words. The data is

divided into fields, which includes a message identifier, a time

stamp, a byte count, up to 8 bytes of data, and several control

bits. Each node monitors the messages being passed on the net-

work. If the identifier in the transmitted message matches an

identifier in one of its mailboxes, the module knows that the

message was meant for it, passes the data into its appropriate

mailbox, and signals the processor of message arrival with an

interrupt.

The CAN controller can wake up the processor from sleep mode

upon generation of a wake-up event, such that the processor can

be maintained in a low-power mode during idle conditions.

Additionally, a CAN wake-up event can wake up the on-chip

internal voltage regulator from the powered-down

hibernate state.

The electrical characteristics of each network connection are

very stringent. Therefore, the CAN interface is typically divided

into two parts: a controller and a transceiver. This allows a sin-

gle controller to support different drivers and CAN networks.

The ADSP-BF50x CAN module represents the controller part of

the interface. This module’s network I/O is a single transmit

output and a single receive input, which connect to a line

transceiver.

The CAN clock is derived from the processor system clock

(SCLK) through a programmable divider and therefore does not

require an additional crystal.

TWI CONTROLLER INTERFACE

The processors include a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is compatible with the widely used

bus standard. The TWI module offers the capabilities of

simultaneous master and slave operation, support for both 7-bit

addressing and multimedia data arbitration. The TWI interface

utilizes two pins for transferring clock (SCL) and data (SDA)

and supports the protocol at speeds up to 400K bits/sec. The

TWI interface pins are compatible with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

PORTS

Because of the rich set of peripherals, the processor groups the

many peripheral signals to three ports—Port F, Port G, and

Port H. Most of the associated pins are shared by multiple sig-

nals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The processor has 35 bidirectional, general-purpose I/O (GPIO)

pins allocated across three separate GPIO modules—PORTFIO,

PORTGIO, and PORTHIO, associated with Port F, Port G, and

Port H, respectively. Each GPIO-capable pin shares functional-

ity with other processor peripherals via a multiplexing scheme;

however, the GPIO functionality is the default state of the device

upon power-up. Neither GPIO output nor input drivers are

active by default. Each general-purpose port pin can be individ-

ually controlled by manipulation of the port control, status, and

interrupt registers:

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a differ-

ent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 volt core supply voltage, the

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power

Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

Rev. A | Page 14 of 80 | July 2011

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF50x Blackfin Pro-

cessor Hardware Reference.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally, an external event wakes up the processor. When in the

sleep mode, asserting a wakeup enabled in the SIC_IWRx regis-

ters causes the processor to sense the value of the BYPASS bit in

the PLL control register (PLL_CTL). If BYPASS is disabled, the

processor transitions to the full on mode. If BYPASS is enabled,

the processor transitions to the active mode.

DMA accesses to L1 memory are not supported in sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals

may still be running but cannot access internal resources or

external memory. This powered-down mode can only be exited

by assertion of the reset pin (RESET

). Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the peripherals (SCLK). This setting sets the internal power sup-

ply voltage (V

DDINT

) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (for

example, memory contents, register contents, and other infor-

mation) must be written to a non-volatile storage device prior to

removing power if the processor state is to be preserved.

Writing 0 to the HIBERNATE bit causes EXT_WAKE to transi-

tion low, which can be used to signal an external voltage

regulator to shut down.

Since V

DDEXT

can still be supplied in this mode, all of the exter-

nal pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to still

have power applied without drawing unwanted current.

The processor can be woken up by asserting the RESET

pin. All

hibernate wakeup events initiate the hardware reset sequence.

Individual sources are enabled by the VR_CTL register. The

EXT_WAKE signal indicates the occurrence of a wakeup event.

As long as V

DDEXT

is applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state.

Power Savings

As shown in Table 5, the processor supports three different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. By isolat-

ing the internal logic of the processor into its own power

domain, separate from other I/O, the processor can take advan-

tage of dynamic power management without affecting the other

I/O devices. There are no sequencing requirements for the vari-

ous power domains, but all domains must be powered

according to the appropriate Processor—Specifications table for

processor operating conditions; even if the feature/peripheral is

not used.

The dynamic power management feature of the processor

allows both the processor’s input voltage (V

DDINT

) and clock fre-

quency (f

CCLK

) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Table 4. Power Settings

Mode/State PLL

PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full On Enabled No Enabled Enabled On

Active Enabled/

Disabled

Yes Enabled Enabled On

Sleep Enabled — Disabled Enabled On

Deep Sleep Disabled — Disabled Disabled On

Hibernate Disabled — Disabled Disabled Off

Table 5. Power Domains

Power Domain Power Supply

All internal logic, except Memory V

DDINT

Flash Memory V

DDFLASH

All other I/O V

DDEXT

ADC digital supply

(Logic, I/O)

On ADSP-BF506F processor only.

, V

DRIVE

ADC analog supply

Power Savings Factor

CCLKRED

CCLKNOM

--------------------------

DDINTRED

DDINTNOM

--------------------------------





RED

NOM

---------------









Rev. A | Page 15 of 80 | July 2011

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

where the variables in the equations are:

CCLKNOM

is the nominal core clock frequency

CCLKRED

is the reduced core clock frequency

DDINTNOM

is the nominal internal supply voltage

DDINTRED

is the reduced internal supply voltage

NOM

is the duration running at f

CCLKNOM

RED

is the duration running at f

CCLKRED

ADSP-BF50x VOLTAGE REGULATION

The ADSP-BF50x processors require an external voltage regula-

tor to power the V

DDINT

domain. To reduce standby power

consumption, the external voltage regulator can be signaled

through EXT_WAKE to remove power from the processor core.

This signal is high-true for power-up and may be connected

directly to the low-true shut-down input of many common

regulators.

While in the hibernate state, all external supplies (V

DDEXT

DDFLASH

) can still be applied, eliminating the need for external

buffers. The external voltage regulator can be activated from

this power down state by asserting the RESET

pin, which then

initiates a boot sequence. EXT_WAKE indicates a wakeup to

the external voltage regulator.

The power good (PG

) input signal allows the processor to start

only after the internal voltage has reached a chosen level. In this

way, the startup time of the external regulator is detected after

hibernation. For a complete description of the power good

functionality, refer to the ADSP-BF50x Blackfin Processor Hard-

ware Reference.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 4. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the

500 kΩ range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 4 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 4 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in (EE-168) Using Third Overtone

Crystals with the ADSP-218x DSP on the Analog Devices web-

site (www.analog.com)—use site search on “EE-168.”

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 5, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable multiplication factor

(bounded by specified minimum and maximum VCO frequen-

cies). The default multiplier is 6×, but it can be modified by a

software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages V

DDINT

and V

DDEXT

;

the VCO is always permitted to run up to the CCLK frequency

specified by the part’s speed grade. The EXTCLK pin can be

configured to output either the SCLK frequency or the input

buffered CLKIN frequency, called CLKBUF. When configured

to output SCLK (CLKOUT), the EXTCLK pin acts as a refer-

ence signal in many timing specifications. While active by

default, it can be disabled using the EBIU_AMGCTL register.

% Power Savings 1 Power Savings Factor–()100%×=

Figure 4. External Crystal Connections

CLKIN

CLKOUT (SCLK)

XTAL

SELECT

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

18 pF *

330 ⍀*

Blackfin Processor

560 ⍀

EXTCLK

Rev. A | Page 16 of 80 | July 2011

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f

SCLK

. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

The maximum CCLK frequency both depends on the part’s

speed grade and depends on the applied V

DDINT

voltage. See

Table 14 for details. The maximal system clock rate (SCLK)

depends on the applied V

DDINT

and V

DDEXT

voltages (see

Table 16).

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by the BMODE input pins dedi-

cated to this purpose. There are two categories of boot modes.

In master boot modes, the processor actively loads data from

parallel or serial memories. In slave boot modes, the processor

receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time.

Some boot modes require a boot host wait (HWAIT) signal,

which is a GPIO output signal that is driven and toggled by the

boot kernel at boot time. If pulled high through an external pull-

up resistor, the HWAIT signal behaves active high and will be

driven low when the processor is ready for data. Conversely,

when pulled low, HWAIT is driven high when the processor is

ready for data. When the boot sequence completes, the HWAIT

pin can be used for other purposes. The BMODE pins of the

reset configuration register, sampled during power-on resets

and software-initiated resets, implement the modes shown in

Table 8.

• IDLE State / No Boot (BMODE = 0x0)—In this mode, the

boot kernel transitions the processor into Idle state. The

processor can then be controlled through JTAG for recov-

ery, debug, or other functions.

• Boot from stacked parallel flash in 16-bit asynchronous

mode (BMODE = 0x1)—In this mode, conservative timing

parameters are used to communicate with the flash device.

The boot kernel communicates with the flash device

asynchronously.

• Boot from stacked parallel flash in 16-bit synchronous

mode (BMODE = 0x2)—In this mode, fast timing parame-

ters are used to communicate with the flash device. The

boot kernel configures the flash device for synchronous

burst communication and boots from the flash

synchronously.

Figure 5. Frequency Modification Methods

Table 6. Example System Clock Ratios

Signal Name

SSEL3–0

Divider Ratio

VCO/SCLK

Example Frequency Ratios

(MHz)

VCO SCLK

0001 1:1 50 50

0110 6:1 300 50

1010 10:1 400 40

Table 7. Core Clock Ratios

Signal Name

CSEL1–0

Divider Ratio

VCO/CCLK

Example Frequency Ratios

(MHz)

VCO CCLK

00 1:1 300 300

01 2:1 300 150

10 4:1 400 100

11 8:1 200 25

PLL

0.5u

to 64u

÷1to15

÷1,2,4,8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK d CCLK

Table 8. Booting Modes

BMODE2–0 Description

000 Idle/No Boot

001 Boot from internal parallel flash in async mode

This boot mode applies to ADSP-BF504F and ADSP-BF506F processors only.

010 Boot from internal parallel flash in sync mode

011 Boot through SPI0 master from SPI memory

100 Boot through SPI0 slave from host device

101 Boot through PPI from host

110 Reserved

111 Boot through UART0 slave from host device

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