PCI Express Base Specification Revision 2.0

需积分: 5 190 浏览量更新于2024-07-09 收藏 3.95MB PDF 举报

"PCI Express Base Specification Revision 2.0 是一份关于PCI Express接口技术的详细规范，涵盖了2006年12月20日的修订版本。此规范旨在定义PCI Express接口的基础架构，包括其数据传输、链接管理、错误处理和配置机制等多个方面。文档的修订历史显示了多次更新，以增强功能和解决已知问题，如信任配置空间、链路速度管理、PCI Express能力结构扩展、链路带宽通知机制、完成超时控制能力、功能级别重置（FLR）以及PCI Express访问控制服务（ACS）等。" PCI Express（Peripheral Component Interconnect Express），简称PCIe，是一种高速接口标准，用于连接计算机系统中的外部设备，如显卡、网卡和硬盘等。在Revision 2.0版本中，PCIe接口的带宽得到显著提升，提供了比前一代更高的数据传输速率，例如，PCIe 2.0 x16接口的理论最大数据传输速率为16GBps（1GBps = 10^9位每秒），是PCIe 1.0的两倍。 PCIe接口采用了串行传输方式，相比于传统的并行PCI总线，它能提供更高的数据传输效率和更低的信号干扰。该规范中的关键概念包括： 1. **信道（Lane）与宽度**: PCIe接口由多个独立的信道组成，每个信道可以双向传输数据。接口的宽度如x1、x8、x16等决定了总的数据传输能力。 2. **链路层（Link Layer）**: 管理数据传输速率的动态调整，包括速度管理和带宽通知机制，确保设备在不同负载下都能高效工作。 3. **配置空间（Configuration Space）**: 用于设备初始化和配置，包括设备识别、中断分配等功能。在Revision 2.0中，增加了信任配置空间，增强了系统的安全性。 4. **错误处理**: 包括完成超时控制能力，当传输出现问题时，能够及时发现并处理，提高系统稳定性。 5. **功能级别重置（Function Level Reset, FLR）**: 允许对单个设备功能进行重置，而不是整个设备，从而提高了系统的灵活性和故障恢复能力。 6. **访问控制服务（Access Control Services, ACS）**: 提供了对PCI Express设备访问的控制，增强了系统的安全性和隔离性。 7. **ECN/ECR**: 表示工程变更通知和工程变更请求，这些更新反映了技术改进和修复，以优化PCI Express规范的实施。总体而言，PCI Express Base Specification Revision 2.0 是一个重要的技术文档，它定义了PCI Express 2.0接口的规范，推动了高性能计算和存储设备的发展，提升了系统的扩展性和兼容性。对于硬件开发者、系统集成商和IT专业人士来说，理解这份规范是至关重要的，以便于设计和维护支持PCIe 2.0标准的系统和设备。

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

Tables

TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 48

ABLE 2-2: FMT[1:0] FIELD VALUES ............................................................................................ 52

TABLE 2-3: FMT[1:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 53

ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 54

ABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 57

TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 57

TABLE 2-7: HEADER FIELD LOCATIONS FOR ID ROUTING............................................................. 58

TABLE 2-8: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 60

ABLE 2-9: ORDERING ATTRIBUTES ............................................................................................. 64

ABLE 2-10: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 65

TABLE 2-11: DEFINITION OF TC FIELD ENCODINGS...................................................................... 65

TABLE 2-12: MESSAGE ROUTING.................................................................................................. 70

TABLE 2-13: INTX MECHANISM MESSAGES ................................................................................. 71

TABLE 2-14: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 73

TABLE 2-15: POWER MANAGEMENT MESSAGES........................................................................... 75

TABLE 2-16: ERROR SIGNALING MESSAGES ................................................................................. 75

TABLE 2-17 UNLOCK MESSAGE.................................................................................................... 77

TABLE 2-18: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 77

TABLE 2-19: VENDOR_DEFINED MESSAGES................................................................................. 79

TABLE 2-20: IGNORED MESSAGES ................................................................................................ 80

TABLE 2-21: COMPLETION STATUS FIELD VALUES....................................................................... 82

TABLE 2-22: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES............................ 96

TABLE 2-23: CALCULATING LOWER ADDRESS FROM 1

DW BE................................................. 97

TABLE 2-24: ORDERING RULES SUMMARY TABLE...................................................................... 102

TABLE 2-25: TC TO VC MAPPING EXAMPLE .............................................................................. 110

TABLE 2-26: FLOW CONTROL CREDIT TYPES ............................................................................. 113

TABLE 2-27: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 114

TABLE 2-28: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 115

ABLE 2-29: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 122

ABLE 2-30: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 122

TABLE 2-31: MAPPING OF BITS INTO ECRC FIELD ..................................................................... 125

TABLE 3-1: DLLP TYPE ENCODINGS.......................................................................................... 143

ABLE 3-2: MAPPING OF BITS INTO CRC FIELD.......................................................................... 146

TABLE 3-3: MAPPING OF BITS INTO LCRC FIELD ....................................................................... 150

TABLE 3-4: UNADJUSTED REPLAY_TIMER LIMITS FOR 2.5 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 155

TABLE 3-5: UNADJUSTED REPLAY_TIMER LIMITS FOR 5.0 GT/S MODE OPERATION BY LINK

WIDTH AND MAX_PAYLOAD_SIZE (SYMBOL TIMES) TOLERANCE: -0%/+100%................. 155

TABLE 3-6: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 2.5 GT/S MODE

OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................... 166

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

TABLE 3-7: ACK TRANSMISSION LATENCY LIMIT AND ACKFACTOR FOR 5.0 GT/S MODE

OPERATION BY LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES)................................... 166

TABLE 4-1: SPECIAL SYMBOLS ................................................................................................... 171

ABLE 4-2: TS1 ORDERED SET ................................................................................................... 178

ABLE 4-3: TS2 ORDERED SET ................................................................................................... 181

TABLE 4-4: ELECTRICAL IDLE ORDERED SET (EIOS) ................................................................ 183

TABLE 4-5: ELECTRICAL IDLE EXIT SEQUENCE ORDERED SET (EIEOS) FOR DATA RATES

GREATER THAN 2.5 GT/S)................................................................................................... 184

ABLE 4-6: ELECTRICAL IDLE INFERENCE CONDITIONS.............................................................. 185

ABLE 4-7: LINK STATUS MAPPED TO THE LTSSM................................................................... 193

TABLE 4-8: PCI EXPRESS 2.5 GT/S / 5.0 GT/S INTEROPERABILITY MATRIX ............................... 246

TABLE 4-9: 2.5 AND 5.0 GT/S TRANSMITTER SPECIFICATIONS ................................................... 252

TABLE 4-10: 5.0 GT/S LIMITS FOR COMMON REFCLK RX ARCHITECTURE.................................. 268

ABLE 4-11: 5.0 GT/S TOLERANCING LIMITS FOR DATA CLOCKED RX ARCHITECTURE............ 269

ABLE 4-12: 2.5 AND 5.0 GT/S RECEIVER SPECIFICATIONS ........................................................ 271

TABLE 4-13: WORST CASE TX CORNERS FOR CHANNEL SIMULATION........................................ 287

TABLE 4-14: FILTERING FUNCTIONS APPLIED TO REFCLK MEASUREMENTS .............................. 292

TABLE 4-15: DIFFERENCE FUNCTION PARAMETERS APPLIED TO REFCLK MEASUREMENT ......... 294

TABLE 4-16: REFCLK PARAMETERS FOR COMMON REFCLK RX ARCHITECTURE AT 5.0 GT/S..... 294

TABLE 4-17: PLL PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE ................................. 296

TABLE 4-18: REFCLK PARAMETERS FOR DATA CLOCKED RX ARCHITECTURE ........................... 296

TABLE 5-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES........................... 322

TABLE 5-2: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK AND COMPONENTS .. 327

TABLE 5-3: ENCODING OF THE ASPM SUPPORT FIELD ............................................................... 352

TABLE 5-4: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION BIT......................................... 353

TABLE 5-5: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION BIT .................................. 353

TABLE 5-6: ENCODING OF THE L0S EXIT LATENCY FIELD .......................................................... 353

TABLE 5-7: ENCODING OF THE L1 EXIT LATENCY FIELD ............................................................ 354

TABLE 5-8: ENCODING OF THE ENDPOINT L0S ACCEPTABLE LATENCY FIELD............................ 354

TABLE 5-9: ENCODING OF THE ENDPOINT L1 ACCEPTABLE LATENCY FIELD.............................. 355

ABLE 5-10: ENCODING OF THE ASPM CONTROL FIELD............................................................ 355

TABLE 5-11: POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS ....................................... 357

ABLE 6-1: ERROR MESSAGES.................................................................................................... 367

ABLE 6-2: PHYSICAL LAYER ERROR LIST ................................................................................. 379

TABLE 6-3: DATA LINK LAYER ERROR LIST............................................................................... 379

TABLE 6-4: TRANSACTION LAYER ERROR LIST .......................................................................... 380

ABLE 6-5: ELEMENTS OF HOT-PLUG ......................................................................................... 410

TABLE 6-6: ATTENTION INDICATOR STATES ............................................................................... 411

ABLE 6-7: POWER INDICATOR STATES ...................................................................................... 412

TABLE 6-8: ACS P2P REQUEST REDIRECT AND ACS P2P EGRESS CONTROL INTERACTIONS..... 434

TABLE 7-1: ENHANCED CONFIGURATION ADDRESS MAPPING .................................................... 442

ABLE 7-2: REGISTER AND REGISTER BIT-FIELD TYPES............................................................. 449

TABLE 7-3: COMMAND REGISTER ............................................................................................... 452

ABLE 7-4: STATUS REGISTER .................................................................................................... 455

ABLE 7-5: SECONDARY STATUS REGISTER ............................................................................... 462

ABLE 7-6: BRIDGE CONTROL REGISTER.................................................................................... 463

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

TABLE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS ............... 465

TABLE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS ........ 466

TABLE 7-9: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................... 468

ABLE 7-10: PCI EXPRESS CAPABILITIES REGISTER................................................................... 470

ABLE 7-11: DEVICE CAPABILITIES REGISTER............................................................................ 473

TABLE 7-12: DEVICE CONTROL REGISTER.................................................................................. 478

TABLE 7-13: DEVICE STATUS REGISTER ..................................................................................... 484

TABLE 7-14: LINK CAPABILITIES REGISTER................................................................................ 487

ABLE 7-15: LINK CONTROL REGISTER ...................................................................................... 492

ABLE 7-16: LINK STATUS REGISTER ......................................................................................... 498

TABLE 7-17: SLOT CAPABILITIES REGISTER ............................................................................... 501

TABLE 7-18: SLOT CONTROL REGISTER...................................................................................... 504

TABLE 7-19: SLOT STATUS REGISTER......................................................................................... 507

ABLE 7-20: ROOT CONTROL REGISTER..................................................................................... 509

ABLE 7-21: ROOT CAPABILITIES REGISTER............................................................................... 511

TABLE 7-22: ROOT STATUS REGISTER........................................................................................ 512

TABLE 7-23: DEVICE CAPABILITIES 2 REGISTER......................................................................... 513

TABLE 7-24: DEVICE CONTROL 2 REGISTER................................................................................ 515

TABLE 7-25: LINK CONTROL 2 REGISTER ................................................................................... 517

TABLE 7-26: LINK STATUS 2 REGISTER ...................................................................................... 523

TABLE 7-27: PCI EXPRESS ENHANCED CAPABILITY HEADER..................................................... 525

TABLE 7-28: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER......................... 527

TABLE 7-29: UNCORRECTABLE ERROR STATUS REGISTER ......................................................... 528

TABLE 7-30: UNCORRECTABLE ERROR MASK REGISTER............................................................ 529

TABLE 7-31: UNCORRECTABLE ERROR SEVERITY REGISTER ...................................................... 532

TABLE 7-32: CORRECTABLE ERROR STATUS REGISTER.............................................................. 533

TABLE 7-33: CORRECTABLE ERROR MASK REGISTER................................................................. 534

TABLE 7-34: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER.................................. 535

TABLE 7-35: HEADER LOG REGISTER ......................................................................................... 536

TABLE 7-36: ROOT ERROR COMMAND REGISTER ....................................................................... 537

ABLE 7-37: ROOT ERROR STATUS REGISTER ............................................................................ 539

TABLE 7-38: ERROR SOURCE IDENTIFICATION REGISTER ........................................................... 541

ABLE 7-39: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER........................................... 544

ABLE 7-40: PORT VC CAPABILITY REGISTER 1......................................................................... 545

TABLE 7-41: PORT VC CAPABILITY REGISTER 2......................................................................... 547

TABLE 7-42: PORT VC CONTROL REGISTER ............................................................................... 548

ABLE 7-43: PORT VC STATUS REGISTER .................................................................................. 549

TABLE 7-44: VC RESOURCE CAPABILITY REGISTER................................................................... 549

ABLE 7-45: VC RESOURCE CONTROL REGISTER....................................................................... 551

TABLE 7-46: VC RESOURCE STATUS REGISTER.......................................................................... 554

TABLE 7-47: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE ..................... 555

ABLE 7-48: LENGTH OF THE VC ARBITRATION TABLE ............................................................. 555

TABLE 7-49: LENGTH OF PORT ARBITRATION TABLE ................................................................. 557

ABLE 7-50: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER .................................. 558

ABLE 7-51: SERIAL NUMBER REGISTER.................................................................................... 559

ABLE 7-52: ROOT COMPLEX LINK DECLARATION ENHANCED CAPABILITY HEADER ............... 562

PCI EXPRESS BASE SPECIFICATION, REV. 2.0

TABLE 7-53: ELEMENT SELF DESCRIPTION REGISTER ................................................................. 563

TABLE 7-54: LINK DESCRIPTION REGISTER ................................................................................ 564

TABLE 7-55: LINK ADDRESS FOR LINK TYPE 1 ........................................................................... 566

ABLE 7-56: ROOT COMPLEX INTERNAL LINK CONTROL ENHANCED CAPABILITY HEADER ...... 569

ABLE 7-57: ROOT COMPLEX LINK CAPABILITIES REGISTER ..................................................... 570

TABLE 7-58: ROOT COMPLEX LINK CONTROL REGISTER............................................................ 572

TABLE 7-59: ROOT COMPLEX LINK STATUS REGISTER............................................................... 573

TABLE 7-60: POWER BUDGETING ENHANCED CAPABILITY HEADER .......................................... 575

ABLE 7-61: POWER BUDGETING DATA REGISTER..................................................................... 576

ABLE 7-62: POWER BUDGET CAPABILITY REGISTER................................................................. 578

TABLE 7-63: ACS EXTENDED CAPABILITY HEADER................................................................... 579

TABLE 7-64: ACS CAPABILITY REGISTER................................................................................... 580

TABLE 7-65: ACS CONTROL REGISTER ...................................................................................... 581

ABLE 7-66: EGRESS CONTROL VECTOR .................................................................................... 583

ABLE 7-67: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION ENHANCED

CAPABILITY HEADER........................................................................................................... 585

TABLE 7-68: MFVC ENHANCED CAPABILITY HEADER............................................................... 588

TABLE 7-69: PORT VC CAPABILITY REGISTER 1......................................................................... 590

TABLE 7-70: PORT VC CAPABILITY REGISTER 2......................................................................... 591

TABLE 7-71: PORT VC CONTROL REGISTER ............................................................................... 592

TABLE 7-72: PORT VC STATUS REGISTER .................................................................................. 593

TABLE 7-73: VC RESOURCE CAPABILITY REGISTER................................................................... 594

TABLE 7-74: VC RESOURCE CONTROL REGISTER....................................................................... 595

TABLE 7-75: VC RESOURCE STATUS REGISTER.......................................................................... 598

TABLE 7-76: LENGTH OF FUNCTION ARBITRATION TABLE ......................................................... 599

TABLE 7-77: VENDOR-SPECIFIC ENHANCED CAPABILITY HEADER............................................. 601

TABLE 7-78: VENDOR-SPECIFIC HEADER.................................................................................... 602

TABLE 7-79: RCRB HEADER ENHANCED CAPABILITY HEADER................................................. 604

TABLE 7-80: VENDOR ID AND DEVICE ID................................................................................... 605

TABLE 7-81: RCRB CAPABILITIES.............................................................................................. 605

ABLE 7-82: RCRB CONTROL .................................................................................................... 606

TABLE A-1: ISOCHRONOUS BANDWIDTH RANGES AND GRANULARITIES.................................... 609

ABLE B-1: 8B/10B DATA SYMBOL CODES................................................................................. 617

ABLE B-2: 8B/10B SPECIAL CHARACTER SYMBOL CODES ........................................................ 625

剩余641页未读，继续阅读

多拉格D

粉丝: 0
资源: 10

PCI Express Base Specification Revision 2.0

PCI_Express_Base_Rev_2.0.pdf

PCIe规范各版本合集，包括PCI-Express-Base 1.0a、2.0、2.1、3.0、4.0、5.0 六个版本.zip

PCI_Express_Base_Rev_2.0_20Dec06a.rar_PCI Express 2.0 pudn_PCI e

PCI_Express_Base_4.0r0.7.rar_PCI_Express_Base_pci express base_p

PCI_Express_Base_Specification_Revision2.0.pdf

PCI_Express_M_PCI_Express_M.2_pciexpressm.2_PCI_Express_M_2_plea

NCB-PCI_Express_Base_7.0_Rev_0.3.pdf

PCI.Express.Base.Specification.v2.0.pdf

PCI_Express_M.2_Spec_Rev5.1_05012024_NCB.pdf

PCI_Express_M.2_Spec_Rev4.2_0327024_NCB.pdf

最新资源