ISP1504: 高速USB OTG收发器

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"ISP1504ABS - 高速通用串行总线OTG收发器" ISP1504是一款高性能的通用串行总线（USB）On-The-Go（OTG）收发器，它完全符合USB规范2.0版、OTG对USB2.0规范1.2版的补充以及UTMI+低引脚接口（ULPI）规范1.1版。这款收发器能够在高速（480Mbit/s）、全速（12Mbit/s）和低速（1.5Mbit/s）模式下传输和接收USB数据，为USB主机、外设和OTG设备提供了一个引脚优化的物理层前端连接。在便携式电子设备中，如移动电话、数码相机、数码摄像机、个人数字助手（PDAs）和数字音频播放器，ISP1504被广泛使用。它使USB应用特定集成电路（ASICs）、可编程逻辑器件（PLDs）以及任何系统芯片组能够通过12引脚接口与USB的物理层进行通信。这种设计允许设备在数字I/O电压1.65V到3.6V范围内与链路接口，提供了宽泛的工作电压适应性。 ISP1504采用HVQFN32封装，这使得它在空间有限的电子设计中具有良好的集成能力。其主要特性包括： 1. 完全兼容USB规范2.0，确保了与各种USB设备的互操作性。 2. 支持OTG功能，使得设备可以在主机和设备角色之间灵活切换，满足现代多功能设备的需求。 3. 高速数据传输能力，最高可达480Mbit/s，适用于大数据量传输的应用场景。 4. 兼容全速和低速模式，保证了对老式USB设备的兼容性。 5. 12引脚接口设计，降低了系统的复杂性和成本。 6. 工作电压范围广，增加了设计的灵活性。 7. 提供HVQFN32封装，减小了封装尺寸，有利于实现紧凑型产品设计。 ISP1504的这些特性使其成为实现USB功能的理想选择，无论是在需要高效数据传输的高性能设备中，还是在需要节省空间和简化设计的便携式设备中，都能发挥出色的作用。通过集成ISP1504，开发者可以轻松地将USB功能整合到他们的产品中，同时保证与现有USB生态系统的一致性和兼容性。

Product data sheet Rev. 01 — 19 October 2006 14 of 84

NXP Semiconductors

ISP1504A; ISP1504C

ULPI HS USB OTG transceiver

7.9.16 STP

ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet

or a register write operation. When DIR is asserted, the link can optionally assert STP to

abort the ISP1504, causing it to de-assert DIR in the next clock cycle. A weak pull-up

resistor is incorporated into the STP pin as part of the interface protect feature. For details,

see Section 9.3.1.

The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.

For details on STP usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

7.9.17 NXT

ULPI next data output pin. The ISP1504 holds NXT at LOW, by default. When DIR is LOW

and the link is sending data to the ISP1504, NXT will be asserted to notify the link to

provide the next data byte. When DIR is at HIGH and the ISP1504 is sending data to the

link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not

used for register read data or the RXCMD status update.

The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.

For details on NXT usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

7.9.18 CLOCK

A 60 MHz interface clock to synchronize the ULPI bus. CLOCK can be conﬁgured as input

or output. The ISP1504 provides three clocking options:

• A crystal attached between the XTAL1 and XTAL2 pins.

• A clock driven into the XTAL1 pin, with the XTAL2 pin left ﬂoating.

• A 60 MHz clock driven into the CLOCK pin, with XTAL1 tied to REG1V8 and XTAL2

left ﬂoating.

For details on CLOCK usage, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1

7.9.19 CHIP_SELECT_N

Active LOW chip select pin. If CHIP_SELECT_N is not used, it must be tied to GND. For

more information on using CHIP_SELECT_N, see Section 9.3.3.

7.9.20 GND (die pad)

Global ground signal, except for the charge pump that uses CPGND. The die pad is

exposed on the underside of the package as a ground plate. This acts as a ground to all

circuits in the ISP1504, except the charge pump. To ensure correct operation of the

ISP1504, GND must be soldered to the cleanest ground available.

Product data sheet Rev. 01 — 19 October 2006 16 of 84

NXP Semiconductors

ISP1504A; ISP1504C

ULPI HS USB OTG transceiver

8.1.2 Low-power mode

When the USB is idle, the link can place the ISP1504 into low-power mode (also called

suspend mode). In low-power mode, the data bus deﬁnition changes to that shown in

Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the Function

Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The

ISP1504 will draw only suspend current from the V

supply (see Table 43).

During low-power mode, the clock on XTAL1 may be stopped. The clock must be started

again before asserting STP to exit low-power mode. After exiting low-power mode, the

ISP1504 will send an RXCMD to the link if a change was detected in any interrupt source,

and the change still exists. An RXCMD may not be sent if the interrupt condition is

removed before exiting.

For more information on low-power mode enter and exit protocols, refer to

UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1

DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous

mode, the ISP1504 drives DIR to LOW by default, making the data bus

an input so that the ISP1504 can listen for TXCMDs from the link. The

ISP1504 drives DIR to HIGH only when it has data for the link. When

DIR and NXT are HIGH, the byte on the data bus contains decoded

USB data. When DIR is HIGH and NXT is LOW, the byte contains status

information called RXCMD (receive command). The only exception to

this rule is when the PHY returns register read data, where NXT is also

LOW, replacing the usual RXCMD byte. Every change in DIR causes a

turnaround cycle on the data bus, during which DATA[7:0] is not valid

and must be ignored by the link.

DIR is always asserted during low-power and serial modes.

STP I Stop: In synchronous mode, the link drives STP to HIGH for one cycle

after the last byte of data is sent to the ISP1504. The link can optionally

assert STP to force DIR to be de-asserted.

In low-power and serial modes, the link holds STP at HIGH to wake up

the ISP1504, causing the ULPI bus to return to synchronous mode.

NXT O Next: In synchronous mode, the ISP1504 drives NXT to HIGH to throttle

data. If DIR is LOW, the ISP1504 asserts NXT to notify the link to place

the next data byte on DATA[7:0] in the following clock cycle. If DIR is

HIGH, the ISP1504 asserts NXT to notify the link that a valid USB data

byte is on DATA[7:0] in the current cycle. The ISP1504 always drives an

RXCMD when DIR is HIGH and NXT is LOW, unless register read data

is to be returned to the link in the current cycle.

NXT is not used in low-power or serial mode.

Table 4. ULPI signal description

…continued

Signal

name

Direction

on ISP1504

Signal description

Table 5. Signal mapping during low-power mode

Signal Maps to Direction Description

LINESTATE0 DATA0 O combinatorial LINESTATE0 directly driven by analog receiver

LINESTATE1 DATA1 O combinatorial LINESTATE1 directly driven by analog receiver

Product data sheet Rev. 01 — 19 October 2006 17 of 84

NXP Semiconductors

ISP1504A; ISP1504C

ULPI HS USB OTG transceiver

8.1.3 6-pin full-speed or low-speed serial mode

If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]

bus deﬁnition changes to that shown in Table 6. To enter 6-pin serial mode, the link sets

the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial

mode, the link asserts STP. This is provided primarily for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM

For more information on 6-pin serial mode enter and exit protocols, refer to

UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1

8.1.4 3-pin full-speed or low-speed serial mode

If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504 to 3-pin serial mode. In 3-pin serial mode, the data bus

deﬁnition changes to that shown in Table 7. To enter 3-pin serial mode, the link sets the

3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial

mode, the link asserts STP. This is primarily provided for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM

For more information on 3-pin serial mode enter and exit protocols, refer to

UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1

Reserved DATA2 O reserved; the ISP1504 will drive this pin to LOW

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked

interrupt occurs

Reserved DATA[7:4] O reserved; the ISP1504 will drive this pin to LOW

Table 5. Signal mapping during low-power mode

…continued

Signal Maps to Direction Description

Table 6. Signal mapping for 6-pin serial mode

Signal Maps to Direction Description

TX_ENABLE DATA0 I active HIGH transmit enable

TX_DAT DATA1 I transmit differential data on DP and DM

TX_SE0 DATA2 I transmit single-ended zero on DP and DM

INT DATA3 O active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

RX_DP DATA4 O single-ended receive data from DP

RX_DM DATA5 O single-ended receive data from DM

RX_RCV DATA6 O differential receive data from DP and DM

Reserved DATA7 O reserved; the ISP1504 will drive this pin to LOW

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