"WGI211网卡规格介绍及注意事项"

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The Intel® Ethernet Controller I211 is a small package Ethernet controller with a size of 9 x 9 mm. It features PCIe v2.1 (2.5 GT/s) x1 with Switching Voltage Regulator (iSVR) and Integrated Non-Volatile Memory (iNVM). There are three single port SKUs available, including SerDes, Copper, and Copper IT, with a Value Part option for the Intel® Ethernet Controller I211. One of the key features of the I211 is its platform power efficiency, which includes IEEE 802.3az Energy Efficient Ethernet (EEE) and Proxy support with ECMA-393 and Windows* logo for proxy offload. This Ethernet controller also offers advanced features such as a 0 t, which provides a high level of performance and flexibility. It is important to note that the specifications provided in this datasheet are subject to change without notice and are for reference purposes only. For purchasing inquiries, it is recommended to contact the nearest Intel sales representative. The most recent revision of this datasheet was issued in January 2021 with a Revision Number of 3.4 and Order No. 333017-007.

Ethernet Controller I211 —Introduction

1.7.2 Receive Data Flow

Table 1-12 lists a high level description of all data/control transformation steps needed for receiving

Ethernet packets.

Table 1-12. Receive Data Flow

Step Description

The host creates a descriptor ring and configures one of the I211's receive queues with the address location,

length, head, and tail pointers of the ring (one of available Rx queues).

The host initializes descriptors that point to empty data buffers. The host places these descriptors in the correct

location at the appropriate Rx ring.

3 The host updates the appropriate queue tail pointer (RDT).

The I211's DMA senses a change of a specific RDT and as a result sends a PCIe request to fetch the descriptors

from host memory.

The descriptors content is received in a PCIe read completion and is written to the appropriate location in the

descriptor queue internal cache.

6 A packet enters the Rx MAC. The Rx MAC checks the CRC of the packet.

7 The MAC forwards the packet to an Rx filter.

If the packet matches the pre-programmed criteria of the Rx filtering, it is forwarded to the Rx FIFO. VLAN and

CRC are optionally stripped from the packet and L3/L4 checksum are checked and the destination queue is fixed.

The receive DMA fetches the next descriptor from the internal cache of the appropriate queue to be used for the

next received packet.

After the entire packet is placed into the Rx FIFO, the receive DMA posts the packet data to the location indicated

by the descriptor through the PCIe interface. If the packet size is greater than the buffer size, more descriptors are

fetched and their buffers are used for the received packet.

When the packet is placed into host memory, the receive DMA updates all the descriptor(s) that were used by

packet data.

After enough descriptors are gathered for write back or the interrupt moderation timer expires or the packet

requires immediate forwarding, the receive DMA writes back the descriptor content along with status bits that

indicate the packet information including what off loads were done on that packet.

After the interrupt moderation timer completes or an immediate packet is received, the I211 initiates an interrupt

to the host to indicate that a new received packet is already in host memory.

Host reads the packet data and sends it to the TCP/IP stack for further processing. The host releases the

associated buffers and descriptors once they are no longer in use.

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