MSP430FR系列微控制器用户指南：系统复位、中断与低功耗模式

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MSP430FR_6xx_58xx_59xx家族用户手册是一份由TI（德州仪器）官方发布的文档，主要针对MSP430FR系列的嵌入式微控制器，包括MSP430FR58xx、MSP430FR59xx以及MSP430FR6xx。这份用户指南提供了详尽的系统管理、中断处理、低功耗模式、时钟控制和接口配置等方面的指导。在"系统重置、中断和工作模式，系统控制模块(SYS)"部分，该章节首先介绍了SYS模块的作用，它是微控制器的核心部件，负责管理系统的启动、状态转换以及中断处理。系统重置后，设备会进入特定的初始条件，如所有寄存器清零，外设可能被初始化。非屏蔽中断（NMIs）和可屏蔽中断（Maskable Interrupts，MI）是中断处理的基本类型，NMIs通常用于紧急情况，而MI则可以根据需要屏蔽或触发。 SNMITiming部分涉及到了中断请求的精确时间控制，这对于实时性和性能至关重要。中断处理流程包括中断请求的检测、处理优先级判断以及执行相应服务程序。中断嵌套能力允许在中断处理过程中处理其他中断，而中断向量则定义了中断服务程序的地址，通过这些向量可以快速定位并响应中断源。章节还详细讨论了不同的低功耗模式，包括LPM0至LPM4，以及LPM3.5和LPM4.5（LPMx.5）的特殊功能，这些模式旨在优化电池寿命或延长待机时间。对于低功耗应用设计，文档提供了一系列原则，帮助开发者在满足性能需求的同时最大限度地减少能耗。此外，手册还强调了如何连接未使用的引脚，以及如何配置复位/非屏蔽中断引脚RST/NMI，以确保系统的稳定性和功能正确性。连接JTAG接口的配置也在此部分有所涉及，这对于调试和软件开发来说是必不可少的。 MSP430FR_6xx_58xx_59xx家族用户手册是深入理解并有效利用这些微控制器进行高效能、低功耗嵌入式设计的重要参考资源。无论是硬件配置还是软件开发，这份文档都为用户提供了一站式的解决方案。

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Contents

32.4.15 UCBxIE Register .............................................................................................. 853

32.4.16 UCBxIFG Register ............................................................................................ 855

32.4.17 UCBxIV Register .............................................................................................. 857

33 REF_A............................................................................................................................. 858

33.1 REF_A Introduction....................................................................................................... 859

33.2 Principle of Operation .................................................................................................... 860

33.2.1 Low-Power Operation .......................................................................................... 860

33.2.2 Reference System Requests.................................................................................. 860

33.3 REF_A Registers ......................................................................................................... 862

33.3.1 REFCTL0 Register (offset = 00h) [reset = 0000h] ......................................................... 863

34 ADC12_B ......................................................................................................................... 865

34.1 ADC12_B Introduction ................................................................................................... 866

34.2 ADC12_B Operation...................................................................................................... 868

34.2.1 12-Bit ADC Core ................................................................................................ 868

34.2.2 ADC12_B Inputs and Multiplexer............................................................................. 869

34.2.3 Voltage References ............................................................................................ 869

34.2.4 Auto Power Down .............................................................................................. 870

34.2.5 Sample Frequency Mode Selection .......................................................................... 870

34.2.6 Sample and Conversion Timing .............................................................................. 870

34.2.7 Conversion Memory ............................................................................................ 873

34.2.8 ADC12_B Conversion Modes................................................................................. 874

34.2.9 Operation in LPM3 and LPM4 ................................................................................ 879

34.2.10 Window Comparator .......................................................................................... 879

34.2.11 Using the Integrated Temperature Sensor................................................................. 880

34.2.12 ADC12_B Grounding and Noise Considerations ......................................................... 881

34.2.13 ADC12_B Calibration ......................................................................................... 882

34.2.14 ADC12_B Interrupts .......................................................................................... 882

34.3 ADC12_B Registers ...................................................................................................... 884

34.3.1 ADC12CTL0 Register (offset = 00h) [reset = 0000h] ...................................................... 890

34.3.2 ADC12CTL1 Register (offset = 02h) [reset = 0000h] ...................................................... 892

34.3.3 ADC12CTL2 Register (offset = 04h) [reset = 0020h] ...................................................... 894

34.3.4 ADC12CTL3 Register (offset = 06h) [reset = 0000h] ...................................................... 895

34.3.5 ADC12MEMx Register (x = 0 to 31) ......................................................................... 896

34.3.6 ADC12MCTLx Register (x = 0 to 31) ........................................................................ 897

34.3.7 ADC12HI Register (offset = 0Ah) [reset = 0FFFh] ......................................................... 899

34.3.8 ADC12LO Register (offset = 08h) [reset = 0000h] ......................................................... 899

34.3.9 ADC12IER0 Register (offset = 12h) [reset = 0000h]....................................................... 900

34.3.10 ADC12IER1 Register (offset = 14h) [reset = 0000h] ..................................................... 902

34.3.11 ADC12IER2 Register (offset = 16h) [reset = 0000h] ..................................................... 904

34.3.12 ADC12IFGR0 Register (offset = 0Ch) [reset = 0000h]................................................... 905

34.3.13 ADC12IFGR1 Register (offset = 0Eh) [reset = 0000h] ................................................... 907

34.3.14 ADC12IFGR2 Register (offset = 10h) [reset = 0000h] ................................................... 909

34.3.15 ADC12IV Register (offset = 18h) [reset = 0000h]......................................................... 910

35 Comparator E (COMP_E) Module........................................................................................ 912

35.1 COMP_E Introduction .................................................................................................... 913

35.2 COMP_E Operation ...................................................................................................... 914

35.2.1 Comparator ...................................................................................................... 914

35.2.2 Analog Input Switches ......................................................................................... 914

35.2.3 Port Logic ........................................................................................................ 914

35.2.4 Input Short Switch .............................................................................................. 914

35.2.5 Output Filter ..................................................................................................... 915

35.2.6 Reference Voltage Generator................................................................................. 916

35.2.7 Port Disable Register (CEPD) ................................................................................ 917

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Contents

35.2.8 Comparator_E Interrupts ...................................................................................... 917

35.2.9 Comparator_E Used to Measure Resistive Elements ..................................................... 917

35.3 COMP_E Registers....................................................................................................... 920

35.3.1 CECTL0 Register (offset = 00h) [reset = 0000h] ........................................................... 921

35.3.2 CECTL1 Register (offset = 02h) [reset = 0000h] ........................................................... 922

35.3.3 CECTL2 Register (offset = 04h) [reset = 0000h] ........................................................... 923

35.3.4 CECTL3 Register (offset = 06h) [reset = 0000h] ........................................................... 924

35.3.5 CEINT Register (offset = 0Ch) [reset = 0000h]............................................................. 926

35.3.6 CEIV Register (offset = 0Eh) [reset = 0000h]............................................................... 927

36 LCD_C Controller.............................................................................................................. 928

36.1 LCD_C Introduction....................................................................................................... 929

36.2 LCD_C Operation......................................................................................................... 931

36.2.1 LCD Memory .................................................................................................... 931

36.2.2 LCD Timing Generation........................................................................................ 932

36.2.3 Blanking the LCD ............................................................................................... 933

36.2.4 LCD Blinking..................................................................................................... 933

36.2.5 LCD Voltage And Bias Generation ........................................................................... 934

36.2.6 LCD Outputs..................................................................................................... 937

36.2.7 LCD Interrupts................................................................................................... 938

36.2.8 Static Mode...................................................................................................... 940

36.2.9 2-Mux Mode ..................................................................................................... 941

36.2.10 3-Mux Mode.................................................................................................... 942

36.2.11 4-Mux Mode.................................................................................................... 943

36.2.12 6-Mux Mode.................................................................................................... 944

36.2.13 8-Mux Mode.................................................................................................... 945

36.3 LCD_C Registers ......................................................................................................... 947

36.3.1 LCDCCTL0 Register ........................................................................................... 952

36.3.2 LCDCCTL1 Register ........................................................................................... 954

36.3.3 LCDCBLKCTL Register........................................................................................ 955

36.3.4 LCDCMEMCTL Register....................................................................................... 956

36.3.5 LCDCVCTL Register ........................................................................................... 957

36.3.6 LCDCPCTL0 Register.......................................................................................... 959

36.3.7 LCDCPCTL1 Register.......................................................................................... 959

36.3.8 LCDCPCTL2 Register.......................................................................................... 960

36.3.9 LCDCPCTL3 Register.......................................................................................... 960

36.3.10 LCDCCPCTL Register........................................................................................ 961

36.3.11 LCDCIV Register .............................................................................................. 961

37 Extended Scan Interface (ESI) ............................................................................................ 962

37.1 ESI Introduction ........................................................................................................... 963

37.2 ESI Operation ............................................................................................................. 964

37.2.1 ESI Analog Front End .......................................................................................... 964

37.2.2 ESI Timing State Machine..................................................................................... 971

37.2.3 ESI Pre-Processing and State Storage ...................................................................... 976

37.2.4 TimerA Output Stage........................................................................................... 977

37.2.5 ESI Processing State Machine................................................................................ 978

37.2.6 ESI Debug Register ............................................................................................ 982

37.2.7 ESI Interrupts.................................................................................................... 982

37.2.8 Overview of ESI Applications ................................................................................. 983

37.3 ESI Registers.............................................................................................................. 990

37.3.1 ESIDEBUG1 Register .......................................................................................... 991

37.3.2 ESIDEBUG2 Register .......................................................................................... 991

37.3.3 ESIDEBUG3 Register .......................................................................................... 991

37.3.4 ESIDEBUG4 Register .......................................................................................... 992

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37.3.5 ESIDEBUG5 Register .......................................................................................... 992

37.3.6 ESICNT0 Register .............................................................................................. 993

37.3.7 ESICNT1 Register .............................................................................................. 993

37.3.8 ESICNT2 Register .............................................................................................. 994

37.3.9 ESICNT3 Register .............................................................................................. 994

37.3.10 ESIIV Register ................................................................................................. 995

37.3.11 ESIINT1 Register.............................................................................................. 996

37.3.12 ESIINT2 Register.............................................................................................. 998

37.3.13 ESIAFE Register............................................................................................. 1000

37.3.14 ESIPPU Register ............................................................................................ 1002

37.3.15 ESITSM Register ............................................................................................ 1003

37.3.16 ESIPSM Register ............................................................................................ 1005

37.3.17 ESIOSC Register ............................................................................................ 1006

37.3.18 ESICTL Register ............................................................................................. 1007

37.3.19 ESITHR1 Register ........................................................................................... 1009

37.3.20 ESITHR2 Register ........................................................................................... 1009

37.3.21 ESIDAC1Rx Register (x = 0 to 7) ......................................................................... 1010

37.3.22 ESIDAC2Rx Register (x = 0 to 7) ......................................................................... 1010

37.3.23 ESITSMx Register (x = 0 to 31) ........................................................................... 1011

37.3.24 Extended Scan Interface Processing State Machine Table Entry (ESI Memory) ................... 1013

38 Embedded Emulation Module (EEM).................................................................................. 1014

38.1 Embedded Emulation Module (EEM) Introduction.................................................................. 1015

38.2 EEM Building Blocks.................................................................................................... 1017

38.2.1 Triggers......................................................................................................... 1017

38.2.2 Trigger Sequencer ............................................................................................ 1017

38.2.3 State Storage (Internal Trace Buffer)....................................................................... 1017

38.2.4 Cycle Counter.................................................................................................. 1017

38.2.5 EnergyTrace++™ Technology............................................................................... 1018

38.2.6 Clock Control .................................................................................................. 1018

38.2.7 Debug Modes.................................................................................................. 1018

38.3 EEM Configurations..................................................................................................... 1018

Revision History ...................................................................................................................... 1020

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List of Figures

1-1. BOR, POR, and PUC Reset Circuit...................................................................................... 49

1-2. Interrupt Priority............................................................................................................. 50

1-3. Interrupt Processing........................................................................................................ 52

1-4. Return From Interrupt...................................................................................................... 53

1-5. Operation Modes ........................................................................................................... 57

1-6. Devices Descriptor Table.................................................................................................. 66

1-7. SFRIE1 Register ........................................................................................................... 73

1-8. SFRIFG1 Register.......................................................................................................... 74

1-9. SFRRPCR Register........................................................................................................ 75

1-10. SYSCTL Register .......................................................................................................... 77

1-11. SYSJMBC Register ........................................................................................................ 78

1-12. SYSJMBI0 Register........................................................................................................ 79

1-13. SYSJMBI1 Register........................................................................................................ 79

1-14. SYSJMBO0 Register....................................................................................................... 80

1-15. SYSJMBO1 Register....................................................................................................... 80

1-16. SYSUNIV Register ......................................................................................................... 81

1-17. SYSSNIV Register ......................................................................................................... 81

1-18. SYSRSTIV Register........................................................................................................ 82

2-1. PMM Block Diagram ....................................................................................................... 84

2-2. Voltage Failure and Resulting PMM Actions ........................................................................... 85

2-3. PMM Action at Device Power-Up ........................................................................................ 86

2-4. PMMCTL0 Register ........................................................................................................ 89

2-5. PMMCTL1 Register ........................................................................................................ 90

2-6. PMMIFG Register .......................................................................................................... 91

2-7. PM5CTL0 Register......................................................................................................... 92

3-1. Clock System Block Diagram............................................................................................. 95

3-2. Module Request Clock System........................................................................................... 99

3-3. Oscillator Fault Logic ..................................................................................................... 101

3-4. Switch MCLK From DCOCLK to LFXTCLK ........................................................................... 102

3-5. CSCTL0 Register ......................................................................................................... 104

3-6. CSCTL1 Register ......................................................................................................... 104

3-7. CSCTL2 Register ......................................................................................................... 105

3-8. CSCTL3 Register ......................................................................................................... 106

3-9. CSCTL4 Register ......................................................................................................... 107

3-10. CSCTL5 Register ......................................................................................................... 109

3-11. CSCTL6 Register ......................................................................................................... 110

4-1. MSP430X CPU Block Diagram ......................................................................................... 113

4-2. PC Storage on the Stack for Interrupts ................................................................................ 114

4-3. Program Counter.......................................................................................................... 115

4-4. PC Storage on the Stack for CALLA ................................................................................... 115

4-5. Stack Pointer .............................................................................................................. 116

4-6. Stack Usage............................................................................................................... 116

4-7. PUSHX.A Format on the Stack ......................................................................................... 116

4-8. PUSH SP, POP SP Sequence.......................................................................................... 116

4-9. SR Bits ..................................................................................................................... 117

4-10. Register-Byte and Byte-Register Operation........................................................................... 119

4-11. Register-Word Operation ................................................................................................ 119

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List of Figures

4-12. Word-Register Operation ................................................................................................ 120

4-13. Register – Address-Word Operation ................................................................................... 120

4-14. Address-Word – Register Operation ................................................................................... 121

4-15. Indexed Mode in Lower 64KB........................................................................................... 123

4-16. Indexed Mode in Upper Memory ....................................................................................... 124

4-17. Overflow and Underflow for Indexed Mode ........................................................................... 125

4-18. Example for Indexed Mode.............................................................................................. 126

4-19. Symbolic Mode Running in Lower 64KB .............................................................................. 128

4-20. Symbolic Mode Running in Upper Memory ........................................................................... 129

4-21. Overflow and Underflow for Symbolic Mode .......................................................................... 130

4-22. MSP430 Double-Operand Instruction Format......................................................................... 138

4-23. MSP430 Single-Operand Instructions.................................................................................. 139

4-24. Format of Conditional Jump Instructions .............................................................................. 140

4-25. Extension Word for Register Modes ................................................................................... 143

4-26. Extension Word for Non-Register Modes.............................................................................. 143

4-27. Example for Extended Register or Register Instruction ............................................................. 144

4-28. Example for Extended Immediate or Indexed Instruction ........................................................... 145

4-29. Extended Format I Instruction Formats ................................................................................ 146

4-30. 20-Bit Addresses in Memory ............................................................................................ 146

4-31. Extended Format II Instruction Format................................................................................. 147

4-32. PUSHM and POPM Instruction Format................................................................................ 148

4-33. RRCM, RRAM, RRUM, and RLAM Instruction Format .............................................................. 148

4-34. BRA Instruction Format .................................................................................................. 148

4-35. CALLA Instruction Format ............................................................................................... 148

4-36. Decrement Overlap....................................................................................................... 174

4-37. Stack After a RET Instruction ........................................................................................... 193

4-38. Destination Operand—Arithmetic Shift Left ........................................................................... 195

4-39. Destination Operand—Carry Left Shift................................................................................. 196

4-40. Rotate Right Arithmetically RRA.B and RRA.W ...................................................................... 197

4-41. Rotate Right Through Carry RRC.B and RRC.W .................................................................... 198

4-42. Swap Bytes in Memory................................................................................................... 205

4-43. Swap Bytes in a Register................................................................................................ 205

4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A ................................................................. 232

4-45. Destination Operand-Arithmetic Shift Left ............................................................................. 233

4-46. Destination Operand-Carry Left Shift .................................................................................. 234

4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A ................................................................ 235

4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode.......................................................... 237

4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode.................................................... 237

4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A .............................................................. 239

4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode ........................................................ 241

4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode .................................................. 241

4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A..................................................................... 242

4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode .............................................................. 243

4-55. Swap Bytes SWPBX.A Register Mode ................................................................................ 247

4-56. Swap Bytes SWPBX.A In Memory ..................................................................................... 247

4-57. Swap Bytes SWPBX[.W] Register Mode .............................................................................. 248

4-58. Swap Bytes SWPBX[.W] In Memory ................................................................................... 248

4-59. Sign Extend SXTX.A ..................................................................................................... 249

4-60. Sign Extend SXTX[.W] ................................................................................................... 249

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