RISC-V指令集详解：最新用户级ISA规范

需积分: 1 133 浏览量更新于2024-07-09 收藏 828KB PDF 举报

RISC-V指令集详解是关于RISC-V架构的一份详细文档，该架构是一种开放源代码的精简指令集计算机(RISC)指令集标准。由Andrew Waterman、Yunsup Lee、David A. Patterson和Krste Asanovic四位来自加州大学伯克利分校电气工程与计算机科学系的研究人员共同编写，该文档是用户级别指令集架构版本2.0的官方手册。这份技术报告（UCB/EECS-2014-54）发布于2014年5月6日，并保留所有作者的版权。 RISC-V指令集的设计目标在于提供高性能、可扩展性和灵活性，使其适用于各种应用场景，包括嵌入式系统、物联网(IoT)设备、服务器甚至是超级计算机。它强调简洁的指令集结构，减少指令数量，提高执行效率，同时保持足够的功能来支持现代计算需求。在本手册的第一部分，用户级别ISA (Instruction Set Architecture) 描述了RISC-V的核心概念和设计原则。它包括基础指令集，如数据处理、控制转移、存储操作等，这些指令都是为了简化硬件实现并优化性能。手册还涵盖了指令格式、寻址方式、寄存器体系以及异常处理等内容。 RISC-V指令集特别注重软件可访问性，允许开发者自定义指令，通过添加新的指令扩展（ISA extensions），满足特定应用的需求。这种灵活性使得RISC-V在学术界和工业界都得到了广泛的关注和支持，因为它可以适应不断变化的技术环境。此外，手册还强调了许可证政策，即个人或课堂使用可以自由复制或打印，但商业用途或大规模分发需获得事先许可。这体现了RISC-V开源精神，旨在促进技术创新和社区合作。对于想要深入了解RISC-V指令集的工程师、研究人员和开发者来说，这份手册是宝贵的参考资料，它提供了深入学习和实施RISC-V架构的全面指南。随着后续版本的更新，RISC-V将继续发展，成为未来高性能计算领域的重要选项之一。

6 Volume I: RISC-V User-Level ISA V2.0

extension can map 3 additional 30-bit instruction spaces into the 32-bit ﬁxed-width format, while

preserving support for standard >=32-bit instruction-set extensions. Further, if the implemen-

tation also does not need instructions >32-bits in length, it can recover a further four major

opcodes.

We consider it a feature that any length of instruction containing all zero bits is not legal, as

this quickly traps erroneous jumps into zeroed memory regions.

The base RISC-V ISA has a little-endian memory system, but non-standard variants can provide

a big-endian or bi-endian memory system. Instructions are stored in memory with each 16-bit

parcel stored in a memory halfword according to the implementation’s natural endianness. Parcels

comprising one instruction are stored at increasing halfword addresses, with the lowest addressed

parcel holding the lowest numbered bits in the instruction speciﬁcation, i.e., instructions are always

stored in a little-endian sequence of parcels regardless of the memory system endianness. The code

sequence in Figure 1.2 will store a 32-bit instruction to memory correctly regardless of memory

system endianness.

We chose little-endian byte ordering for the RISC-V memory system because little-endian sys-

tems are currently dominant commercially (all x86 systems; iOS, Android, and Windows for

ARM). A minor point is that we have also found little-endian memory systems to be more nat-

ural for hardware designers. However, certain application areas, such as IP networking, operate

on big-endian data structures, and so we leave open the possibility of non-standard big-endian

or bi-endian systems.

We have to ﬁx the order in which instruction parcels are stored in memory, independent

of memory system endianness, to ensure that the length-encoding bits always appear ﬁrst in

halfword address order. This allows the length of a variable-length instruction to be quickly

determined by an instruction fetch unit by examining only the ﬁrst few bits of the ﬁrst 16-bit

instruction parcel. Once we had decided to ﬁx on a little-endian memory system and instruction

parcel ordering, this naturally led to placing the length-encoding bits in the LSB positions of the

instruction format to avoid breaking up opcode ﬁelds.

1.3 Exceptions, Traps, and Interrupts

We use the term exception to refer to an unusual condition occurring at run time. We use the term

trap to refer to the synchronous transfer of control to a supervisor environment when caused by

an exceptional condition occurring within a RISC-V thread. We use the term interrupt to refer to

the asynchronous transfer of control to a supervisor environment caused by an event outside of the

current RISC-V thread.

The instruction descriptions in following chapters describe conditions that raise an exception dur-

ing execution. Whether and how these are converted into traps is dependent on the execution

environment, though the expectation is that most environments will take a precise trap when an

exception is signaled (except for ﬂoating-point exceptions, which, in the standard ﬂoating-point

extensions, do not cause traps).

Our use of “exception” and “trap” matches that in the IEEE-754 ﬂoating-point standard.

Chapter 2

RV32I Base Integer Instruction Set

This chapter describes the RV32I base integer instruction set. Much of the commentary also applies

to the RV64I variant.

RV32I was designed to be suﬃcient to form a compiler target and to support modern operating

system environments. The ISA was also designed to reduce the hardware required in a minimal

implementation. RV32I contains 47 unique instructions, though an implementation might cover

the eight SCALL/SBREAK/RD* instructions with a single SYSTEM hardware instruction that

always traps, reducing hardware instruction count to 40 total. RV32I can emulate almost any

other ISA extension (except the A extension, which requires additional hardware support for

atomicity).

2.1 Programmers’ Model for Base Integer Subset

Figure 2.1 shows the user-visible state for the base integer subset. There are 31 general-purpose

registers x1–x31, which hold integer values. Register x0 is hardwired to the constant 0. There is

no hardwired subroutine return address link register, but the standard software calling convention

uses register x1 to hold the return address on a call. For RV32, the x registers are 32 bits wide,

and for RV64, they are 64 bits wide. This document uses the term XLEN to refer to the current

width of an x register in bits (either 32 or 64).

There is one additional user-visible register: the program counter pc holds the address of the current

instruction.

The number of available architectural registers can have large impacts on code size, performance,

and energy consumption. Although 16 registers would arguably be suﬃcient for an integer ISA

running compiled code, it is impossible to encode a complete ISA with 16 registers in 16-bit

instructions using a 3-address format. Although a 2-address format would be possible, it would

increase instruction count and lower eﬃciency. We wanted to avoid intermediate instruction

sizes, such as Xtensa’s 24-bit instructions, to simplify base hardware implementations, and once

a 32-bit instruction size was adopted, it was straightforward to support 32 integer registers.

For the base ISA, we chose a conventional size of 32 integer registers for these reasons and

based on the behavior of standard compilers on existing code and on our experience generating

剩余101页未读，继续阅读

steven~~~

粉丝: 2523
资源: 10

RISC-V指令集详解：最新用户级ISA规范

riscv特权指令集

RISC-V intro （ppt）

RISC-V指令集中文.zip

RISC-V架构中如何通过FCVT指令处理浮点到整数的转换溢出？请详细说明转换指令的格式和异常处理。

在RISC-V架构中，浮点到整数的转换指令FCVT是如何处理转换溢出的？并且请详细说明相关指令的格式。

在学习RISC-V蜂鸟E203核心时，如何从基础概念出发理解其设计初衷和应用场景？

在RISC-V架构中，RV32F与RV32D指令集在处理浮点运算时有何不同？它们是如何支持IEEE 754标准的舍入模式的？

RISC-V架构中RV32F与RV32D的区别是什么？它们与IEEE 754标准的舍入模式如何兼容？

RISC-V架构中RV32F与RV32D的浮点运算舍入模式是如何实现的？与IEEE 754标准的兼容性如何？

在RISC-V架构中，如何利用调试模块（DM）的抽象命令功能进行内存的读写操作？

最新资源