Freescale i.MX21 微处理器技术数据手册

需积分: 11 187 浏览量更新于2024-06-30 5 收藏 1.67MB PDF 举报

"NXP-MC9328MX21.pdf是NXP（现为恩智浦半导体）的一份技术数据手册，详细介绍了MC9328MX21微处理器。该芯片主要用于智能手机和便携式产品的市场，提供高性能、低功耗的解决方案。文档版本为Rev.3.4，发布于2010年7月。" NXP的i.MX系列微处理器在便携式手持设备市场中展现出领导地位，而MC9328MX21（简称i.MX21）是这一系列的一个重要成员。该芯片基于ARM926EJ-S™内核，这是一个支持加速Java执行的高性能处理器核心，运行速度可高达266MHz。MC9328MX21旨在满足智能手机和便携式产品的需求，集成了智能外围设备、先进的处理器核心以及电源管理功能。 i.MX21的特性包括： 1. **高性能ARM926EJ-S核心**：这是一款由ARM公司设计的32位RISC处理器，具有高性能和低功耗的特点，适合处理复杂的计算任务，特别是在嵌入式系统中。 2. **智能集成外围设备**：MC9328MX21集成了多种外设，如通信接口、存储控制器、图形处理单元等，减少了外部组件的需求，降低了系统成本和功耗。 3. **高级处理器核心**：ARM926EJ-S内核支持Thumb和ARM指令集，具备Java加速器，提高了软件执行效率，尤其适用于运行Java应用程序。 4. **电源管理**：芯片内置电源管理系统，能够根据工作负载动态调整电压和频率，延长设备的电池寿命。 5. **MAPBGA-289封装**：MC9328MX21采用多层阵列球栅阵列（MAPBGA）封装，共有289个引脚，这种封装方式有利于减小封装尺寸并提高封装密度。 6. **订购信息**：手册中提到，具体的订购信息可以参考第3页的表格1，这通常包括不同的封装选项、温度范围和批号等信息。 7. **SmartSpeed产品家族**：i.MX21属于NXP的SmartSpeed产品线，这些产品提供高性能而保持低能耗，是针对嵌入式应用的优化设计。这份数据手册提供了MC9328MX21的详细电气特性、封装信息、管脚配置、功能描述以及操作指南，是设计基于该处理器系统的工程师的重要参考资料。对于开发智能手机、便携式设备或需要高效能、低功耗解决方案的项目来说，MC9328MX21是一个理想的选择。

MC9328MX21 Technical Data, Rev. 3.4

16 Freescale Semiconductor

Specifications

Table 6 shows the input and output capacitance for the device.

Table 7 shows the power consumption for the device.

3.4 AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All

signals are specified relative to an appropriate edge of other signals. All timing specifications are specified

at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz)

with an operating supply voltage from V

DD min

to V

DD max

under an operating temperature from T

to T

Input leakage current (no pull-up or pull-

down)

= 0 or NVDD – – ±1 μA

I/O leakage current I

I/O

= NVDD or 0

I/O = High impedance

state

––±5μA

1. Data labeled Typical is not guaranteed, but is intended as an indication of the IC's potential performance.

2. For DSCR definition refer to the System Control chapter in the reference manual.

Table 6. Input/Output Capacitance

Parameter Symbol Min Typ Max Units

Input capacitance C

––

5pF

Output capacitance C

––

5pF

Table 7. Power Consumption

ID Parameter Conditions Symbol Typ Max Units

1 Run Current QVDD = QVDDX = 1.65 V, NVDD1 = 1.8 V.

NVDD2 through NVDD6 = VDDA = 3.1V.

Core = 266 MHz, System = 133 MHz.

MPEG4 Playback (QVGA) from MMC/SD card, 30fps,

44.1kHz audio.

QVDD

+ I

QVDDX

120 – mA

NVDD1

8–mA

NVDD2

through I

NVDD6

+ I

VDDA

6.6 – mA

2 Sleep Current Standby current with Well Biasing System enabled.

Well Bias Control Register (WBCR) must be set as

follows:

WBCR:

CRM_WBS bits = 01

CRM_WBFA bit = 1

CRM_WBM bits = 001

CRM_SPA_SEL bit = 1

FMCR bit = 1

For WBCR definition refer to System Control Chapter

in the reference manual.

STBY

QVDD = QVDDX = 1.65V, TA

1. TA = 70°C for suffixes VK, VM, DVK, DVM, and SVK. TA = 85°C for suffixes CVK, CVM, and SCVK.

–3.0mA

QVDD = QVDDX = 1.65V, 25

° – 700 μA

QVDD = QVDDX = 1.55V, 25

° 320 – μA

Table 5. DC Characteristics (Continued)

Parameter Symbol Test Conditions Min Typ

Max Units

Specifications

MC9328MX21 Technical Data, Rev. 3.4

Freescale Semiconductor 17

All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer

to the reference manual’s System Control Chapter for details on drive strength settings.

Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also

known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock

(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and

other signals required to meet 133 MHz timing.

The values shown in Table 8 apply over the recommended operating temperature range. Care must be

taken to minimize parasitic capacitance of associated printed circuit board traces.

3.5 DPLL Timing Specifications

Parameters of the DPLL are given in Table 11. In this table, T

ref

is a reference clock period after the

predivider and T

dck

is the output double clock period.

Table 8. Loading Guidelines for Fast IO Signals to Achieve 133 MHz Operation

Drive Strength Setting (DSCR2–DSCR12) Maximum I/O Loading at 1.8 V Maximum I/O Loading at 3.0 V

000: 3.5 mA 9 pF 12 pF

001: 4.5 mA 12 pF 16 pF

011: 5.5 mA 15 pF 21 pF

111: 6.5 mA 19 pF 26 pF

Table 9. 32k/26M Oscillator Signal Timing

Parameter Minimum RMS Maximum Unit

EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL – 5 20 ns

EXTAL32k input jitter (peak to peak) for MCUPLL only – 5 100 ns

EXTAL32k startup time 800 – – ms

Table 10. CLKO Rise/Fall Time (at 30pF Loaded)

Best Case Typical Worst Case Units

Rise Time 0.80 1.00 1.40 ns

Fall Time 0.74 1.08 1.67 ns

Table 11. DPLL Specifications

Parameter Test Conditions Minimum Typical Maximum Unit

Reference clock frequency range Vcc = 1.5V 16 – 320 MHz

Pre-divider output clock frequency

range

Vcc = 1.5V 16 – 32 MHz

Double clock frequency range Vcc = 1.5V 220 – 560 MHz

Pre-divider factor (PD) – 1 – 16 –

Total multiplication factor (MF) Includes both integer and fractional parts 5 – 15 –

剩余99页未读，继续阅读

不觉明了

粉丝: 4514
资源: 5759

Freescale i.MX21 微处理器技术数据手册

基于MC9328MX21的多功能开发平台研究

1-NXP-Mr. Noy Kucuk.pdf

TP-NXP-AUT-T4041.pdf

100-uCOS-III-NXP-LPC1768-001.pdf

1-NXP-Mr. Noy Kucuk.zip

WINNING-WITH-I.MX-8-AND-I.MX-8X-APPLICATIONS-PROCESSORS.pdf

TP-NXP-AUT-T4077A.pdf

TP-NXP-AUT-T4142A.pdf

TP-NXP-AUT-T4143A.pdf

TP-NXP-IND-T4086A.pdf

最新资源