SB3500 SandBlaster® Baseband Processor DataSheet: Features & Interfaces (V1.5)

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SB3500芯片手册是由WuxiDSP和Optimum Semiconductor Technologies共同开发的一款高性能的Baseband处理器。该产品是SandBlaster®系列的一部分，专为无线通信和信号处理应用设计，旨在提供高效能和低功耗解决方案。此文档的版本为SB3500-PFI-V1.5，于2014年10月21日发布，包含了详细的规格、功能接口描述以及产品特性。手册的核心内容包括： 1. **产品概述**： - SB3500是一款基于SandBlaster®技术的基带处理器，用于处理和优化无线通信中的信号传输，可能应用于移动设备、物联网(IoT)设备和通信基础设施中。 2. **主要功能与接口**： - 提供了详细的接口规范，如APB（Advanced Peripheral Bus）通用目的计数器、I2C通信接口等，以便系统设计师能够有效集成这款处理器到他们的系统架构中。 3. **版本更新历史**： - 从1.0.1版开始，文档经历了多次修订，包括改进文档链接、增强描述、修正错误和添加或删除部分图例，以确保信息的准确性和完整性。 4. **核心组件与特性**： - **Device Power Management Real-Time Clock (RTC)**：着重介绍了实时钟管理模块，对于电池续航和系统时钟的精确控制至关重要。 5. **专有信息与版权**： - Optimum Semiconductor Technologies的联系信息，包括电话和传真号码，表明了文档的所有权和客户服务支持。 6. **安全性与合规性**： - 提到了关于专有信息的部分，强调了可能存在的专利或版权条款，提醒用户在使用时需要遵循相关规定。 SB3500芯片手册是一个全面的技术文档，为工程师提供了关于硬件设计、编程接口和电源管理等方面的关键信息，是开发基于SB3500处理器产品的宝贵参考资料。了解并掌握这个手册，可以有效地利用SB3500处理器来构建高效、稳定且节能的无线通信系统。

Wuxi DSP

Optimum Semiconductor Technologies

SB3500

SandBlaster®

Baseband Processor

Start Addr. Stop Addr. Accessed block

0x88008000 0x88008FFF Camera Interface

0x88009000 0x80009FFF Reserved

0x8800A000 0x8800BFFF Application Processor Interface

0x8800C000 0x8BFFFFFF Reserved

0x8C000000 0x8C000FFF DPMU

0x8C001000 0x8C001FFF GPIO 1

0x8C002000 0x8C002FFF GPIO 2

0x8C003000 0x8C003FFF GPIO 3

0x8C004000 0x8C004FFF GPIO 4

0x8C005000 0x8C005FFF GPIO 5

0x8C006000 0x8C006FFF GPIO 6

0x8C007000 0x8C007FFF GPIO 7

0x8C008000 0x8C008FFF GPIO 8

0x8C009000 0x8C009FFF Reserved

0x8C00A000 0x8C00AFFF APB Counter 1

0x8C00B000 0x8C00BFFF APB Counter 2

0x8C00C000 0x8C00CFFF Smart Card I/F

0x8C00D000 0x8C00DFFF Audio Codec

0x8C00E000 0x8C00EFFF UART1 / Irda

0x8C00F000 0x8C00FFFF UART2

0x8C010000 0x8C010FFF Keyboard & Mouse

0x8C011000 0x8C011FFF I2C

0x8C012000 0x8C012FFF I2S

0x8C013000 0x8C013FFF SPI

0x8C014000 0x8C01FFFF Reserved

0x8C020000 0x8C020FFF SMC Control Registers

0x8C021000 0x8C021FFF DMC Control Registers

0x8C022000 0x8C022FFF Reserved

0x8C023000 0x8C023FFF DigRF

0x8C024000 0x8FFFFFFF Reserved

0x90000000 0x9003FFFF SBX1 internal data Memory

0x90040000 0x9FBFFFF Reserved

0x9FC00000 0x9FC00FFF SBX1 PSDA

0x9FC01000 0x9FC01FFF SBX1 PSDB

0x9FC02000 0x9FC02FFF SBX1 External Interrupt Controller

0x9FC03000 0x9FC03FFF SBX1 Multi-Purpose Timers

Features & Interfaces V1.5

Wuxi DSP / Optimum Semiconductor Technologies Inc.

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Optimum Semiconductor Technologies

SB3500

SandBlaster®

Baseband Processor

Device Peripherals

1 SANDBLASTER® NODE INTERFACE CONTROL REGISTERS

This section describes the registers available to the user for control of the external

interfaces on the SandBlaster® SB3500 Device. It should be noted that the cores are

replicated within the design, and therefore, each core contains identical registers within

their respective local address range. Note that an offset has been provided to describe the

address location for each register. The programmer must add the specified offset to the

base address for the respective core (as described in Section 4). All registers are in a

global address map which can be accessed from any SandBlaster® core or the ARM

926EJ-S.

1.1 NODE PARALLEL STREAMING DATA INTERFACE

The Parallel Streaming Data (PSD) interfaces are used to control input/output data flow

between the SB3500 device and an external device (e.g., an A2D converter). Each

SandBlaster® core has two PSD channels: channel A and channel B. The functions

provided in each PSD channel are:

1. Digital 16-bit parallel input data port, data is captured on the rising and falling

edge of the clock PSD_CLK (typically used for multiplexed I/Q input data);

2. Digital (16-bit) parallel output data port, data is sent on the rising and falling edge

of the clock PSD_CLK (typically used for multiplexed I/Q output data);

There are four sets of bidirectional IO pads that are available for the PSD interfaces. The

first set (PSD1) and second set (PSD2) of IO pads are dedicated to channels A and B of

Node 1, respectively. The third set (PSD3) of IO pads is shared between channel A of

Nodes 2, 3 and other IOs. The fourth set (PSD4) of IO pads is shared between channel B

of Nodes 2, 3 and other IOs. The sharing of the IO pads is controlled using the

Sdc_PsdShare described in Section 3.7.

If the bidirectional IO pads are owned by the PSDs then the direction of the IO pads can

be controlled internally or externally. If the direction is set internally using the

NodeX_Upsd_Ctrl register described in this section, the PSD_DIR pin is an output

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Optimum Semiconductor Technologies

SB3500

SandBlaster®

Baseband Processor

reflecting the direction of the IO pads. If the direction is set externally, the PSD_DIR pin

is an input. The value of the PSD_DIR pin sets the direction of the IO pads.

The DMA transmission and reception can be gated by using timers, the Node Multi-

Purpose Timer, covered in Section 1.7 or the Device Power Management Event Timers,

covered in Section 4.1.8. Please refer to this section for more information on how to use

them together.

1.1.1 DOWNLINK PARALLEL STREAMING DATA DMA CHANNEL

The Downlink Parallel Streaming Data (DPSD) DMA interface provides the mechanism

for capturing streaming data from an external parallel streaming data interface, e.g., an

A2D converter. Data received through the device’s parallel input port is expected in

multiplexed form: I data sampled on the falling edge of the external interface clock; Q

data sampled on the rising edge of the external interface clock. The interface de-

multiplexing and data transfer characteristics to the SandBlaster® core’s data memory (I

and Q buffers) are setup by programming of the control register. The DPSD direction

control is performed using the UPSD control register. Refer to bit 28 of the UPSD control

Example: If DPSD direction has to be controlled from within the SandBlaster® core and

set to input mode (RX of downlink data) then Bit 28 of UPSD control register has to be 0

and bits 31:30 have to be set to 00.

Three registers are used to control DPSD DMA transfers. The base address for these

registers is 0xNFC00000 (where N is 0x9 for SBX1, 0xA for SBX2 and 0xB for SBX3).

The following describes the registers:

NodeX_Dpsd_IAddr (PSDA Offset 0x8, PSDB Offset: 0x1008; Reset: 0x0):

Sets the I data starting address and shows the current I address being accessed.

Position Function

27:0 DPSD I data starting address when written.

DPSD I current address when read.

Features & Interfaces V1.5

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Optimum Semiconductor Technologies

SB3500

SandBlaster®

Baseband Processor

NodeX_Dpsd_QAddr (PSDA Offset 0x10, PSDB Offset: 0x1010; Reset: 0x0):

Sets the Q data starting address and shows the current Q address being accessed.

Position Function

27:0 DPSD Q data starting address.

DPSD Q current address when read.

NodeX_Dpsd_Ctrl (PSDA Offset 0x18, PSDB Offset: 0x1018; Reset: 0x0):

The control register is used to enable the interface, and define the buffer configurations

for the received data.

Name Position Function

EnableI 31

I Data DMA Enable: a 1, enables the DMA, a 0 disables the

DMA.

EnableQ 30

Q Data DMA Enable: a 1 enables the DMA, a 0 disables the

DMA.

Decimation 29:28

Capture Rate Decimation for the input data:

00 Captures all data samples (no decimation)

01 Captures every other sample (decimation by 2)

10 Captures every fourth sample (decimation by 4)

11 Captures every eighth sample (decimation by 8)

BufCount 27:20

These bits define the numbers of buffers to be allocated for each

I and Q transfer. The interface allows the memory allocated for

I and Q data to be partitioned into multiple buffers. This is used

to implement “double/multi buffering” schemes, allowing the

application code to read a buffer while a new buffer is being

written. The application can synchronize its internal operation

via buffer full interrupt flags. An interrupt is generated after

completing the write for each I/Q buffer pair. Note that a

circular buffer is implemented – the starting address will be used

after the total allocated memory space is written. The value to be

written is (# of buffers -1).

Example: if 4 input input buffers needed, bits 27:20 should be

set to 3 (0x03)

PMTimer 19:18 These bits select which Device Power Management Event

Timers controls when data is to be captured on the input

channel. PSDA uses event timers 1 and 3, and PSDB uses event

timers 2 and 4. The selected timer must be programmed to

generate a single or continuous “gating” pulse, which enables

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