AES算法的高效可配置ASIC实现：80.1%频谱提升
需积分: 10 74 浏览量
更新于2024-09-12
收藏 540KB PDF 举报
本文主要探讨了"网络安全与密码学"特别期刊(IJCASpecialIssueon"NetworkSecurityandCryptography")中发表的一篇关于高级加密标准(AES)算法高效应用特定集成电路(ASIC)实现的研究论文。作者P.Saravanan、N.Renuka Devi和G.Swathi来自印度Coimbatore的PSGCT学院电子与通信工程系，他们提出了一个可配置的AES处理器设计。
该研究的核心焦点在于实现AES加密算法的不同密钥长度版本，包括128位、192位和256位，以适应不同的安全需求。这一设计注重效率，采用紧凑的32位输入/输出接口，既处理数据传输也支持密钥交换，提高了系统的灵活性和易用性。
文章的核心技术亮点在于对加密过程中关键操作的优化，如实时的密钥生成策略以及MixColumn和Inverse MixColumn操作的有效运用。通过对GF(2^2)的有限域进行巧妙设计，这些操作在32位AES加密系统中的实现，相比于现有实施方法，带来了高达80.1%的运行频率提升。这表明了作者团队在硬件优化上的深入研究和技术创新。
作者们的ASIC设计使得整个系统的最大运行频率达到了惊人的333MHz，实现了大约10.656 Gbps的高速数据吞吐量，这对于加密密集型应用来说具有显著的优势。这种高吞吐量不仅提升了加密性能，还节省了处理时间，对于需要处理大量数据的实时安全系统具有实际价值。
总结来说，这篇论文是针对AES密码算法在ASIC中的高效实现进行了深入研究，通过优化架构和算法，实现了更高的性能和更低的延迟，为网络通信和信息安全领域的实践提供了有价值的技术参考。其成果对于推动密码学在嵌入式设备和数据中心级应用中的广泛应用具有重要意义。
IJCA Special Issue on “Network Security and Cryptography”
NSC, 2011
1
A High-Throughput ASIC implementation of
Configurable Advanced Encryption Standard (AES)
Processor
P.Saravanan
Member IEEE
Assistant Professor
Department of ECE
PSG CT, Coimbatore, India
N.RenukaDevi, G.Swathi
PG Student
Department of ECE
PSG CT, Coimbatore, India
Dr.P.Kalpana
Professor
Department of ECE
PSG CT, Coimbatore, India
ABSTRACT
This paper proposes the Application Specific Integrated Circuit
(ASIC) implementation of Advanced Encryption Standard
(AES) cryptographic algorithm with reconfigurable 128-bit,
192-bit, 256-bit keys. The proposed implementation has
compact 32-bit I/O for both data and key transfer. By using on
the fly key generation for encryption process along with
efficient implementation of MixColumn and InverseMixColumn
operations using finite field GF(2
2
) for our 32-bit AES crypto
system gives a maximum of 80.1% improvement in operating
frequency when compared to the recent implementations. The
maximum operating frequency of our proposed pipelined
implementation is 333 MHz with high throughput of around
10.656 Gbps in 180 nm standard cell CMOS technology.
Keywords
Keywords - AES, ASIC, Cryptography, Galois Field GF(2
8
), On
the fly key generation, Throughput.
1. INTRODUCTION
Cryptography is the science of using mathematics to encrypt and
decrypt data. Cryptography enables users to store sensitive
information or transmit it across insecure networks (like the
Internet) so that it cannot be read by anyone except the intended
recipient. In order to ensure security in modern wireless
communication systems, many cryptographic algorithms have
been proposed [1]. In 2001, Rijndael algorithm was selected as
the Advanced Encryption Standard (AES) by National Institute
of Standards and Technology (NIST) due to the combination of
security, performance, efficiency, ease of implementation and
flexibility. These features make AES the first choice in many
applications such as Wireless LAN and smart cards [2].
AES can be implemented in both software as well as hardware.
The advantage of a software implementation includes ease of
use, ease of upgrade, portability and flexibility. But the main
drawback of software implementation is the limited physical
security with respect to key storage [3]. Conversely, hardware
implementations are more physically secure, as they cannot be
easily read or modified by an outside attacker. Many hardware
implementations have been proposed for AES in the literature
[4-5]. All these implementations were based on either field
programmable gate arrays (FPGA) or application specific
integrated circuits (ASIC).
In [6], on the fly S-Box values calculation for both encryption
and decryption process has been implemented, which results in
reduced operating frequency due to the increase in critical path
delay. An AES crypto system implementation using high level
code has been discussed in [7]. The maximum throughput
achieved in this design was 2.29 Gbps with 173 K gates in
180nm technology and the maximum operating frequency
obtained was around 154 MHz. A compact 128 MHz AES
implementation has been proposed in [8] which gave a
throughput of around 0.14 Gbps with 5.6 K gates in 180 nm
technology. In [9], two architectures for the AES algorithm have
been proposed through which a maximum throughput of 3.65
Gbps has been achieved. High speed architecture for the
hardware implementation of AES algorithm using combinational
logic S-Box implementation has been presented [10].
In our proposed AES implementation, on the fly key generation
has been used for encryption process. An efficient
implementation has been achieved using finite field GF(2
2
) in
MixColum/InverseMixColumn operations. Shift row and
MixColumn operations are combined together in order to reduce
the number of registers used in both encryption and decryption
process. Pipelining has also been implemented in appropriate
operations to deliver high throughput.
The paper is organized as follows. Section 2 explains the
basic operations in AES algorithm. The complete overview
of the proposed ASIC implementation of AES algorithm is
given in Section 3 followed by the comparison of
experimental results in Section 4. Section 5 concludes the
paper along with noted references.
2. AES ALGORITHM
The AES algorithm is a symmetric block cipher that processes
data blocks of 128 bits using a cipher key of length 128, 192, or
256 bits. Each data block consists of a 4 × 4 array of bytes called
the state, on which the basic operations of the AES algorithm are
performed. The AES encryption and decryption procedures are
shown in Figure 1 and Figure 2. After an initial round key
addition, a round function consisting of four different
transformations SubByte(), ShiftRow(), MixColumn(), and
下载后可阅读完整内容，剩余5页未读，立即下载
点击了解资源详情
点击了解资源详情
点击了解资源详情
2022-07-14 上传
2022-09-22 上传
2022-07-14 上传
2022-09-19 上传
2022-07-14 上传
2022-09-23 上传
