STM32F103xC/E微控制器数据手册：高性能、大容量Flash

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"STM32ZET6是一款高性能的基于ARM Cortex-M3内核的32位微控制器，具有256KB至512KB的闪存、USB、CAN接口、11个定时器、3个ADC和13种通信接口。这款芯片适用于全速生产，并提供了丰富的内存选项和多种外设支持。" STM32F103xC、STM32F103xD和STM32F103xE是STM32系列中的高密度性能线产品。这些微控制器设计用于提供高效的处理能力，具有以下关键特性： 1. **处理器核心**：基于ARM Cortex-M3的32位CPU，最高工作频率可达72MHz，可实现1.25 DMIPS/MHz的性能（以Dhrystone 2.1基准）。内含单周期乘法和硬件除法指令，优化了计算效率。 2. **内存配置**：具备256KB至512KB的闪存存储空间，以及高达64KB的SRAM。此外，集成灵活的静态存储器控制器，支持CompactFlash、SRAM、PSRAM、NOR和NAND等多种类型内存，且带有4个芯片选择信号。 3. **显示支持**：内置LCD并行接口，兼容8080和6800模式，为LCD显示应用提供了便利。 4. **时钟、复位和电源管理**：工作电压范围在2.0V到3.6V之间，包括上电复位（POR）、掉电复位（PDR）和可编程电压检测器（PVD）。还配备了4至16MHz的晶体振荡器、8MHz的工厂校准内部RC振荡器和40kHz的校准内部RC振荡器，以及为RTC和备份寄存器供电的VBAT引脚。 5. **低功耗模式**：支持睡眠、停止和待机三种低功耗模式，VBAT引脚可以为RTC和备份寄存器在主电源断开时继续供电。 6. **模拟特性**：包含3个12位ADC，转换速度可达1μs，最多支持21个通道，为各种模拟信号的数字化提供了高速转换能力。 7. **通信接口**：提供多达13种通信接口，如USB、CAN等，能满足多种连接需求，适合物联网、工业控制和嵌入式系统等应用。 8. **定时器和ADC**：11个定时器可用于计数、PWM输出等多种功能，ADC的快速转换能力使得STM32F103xE适合实时数据采集。 9. **其他外设**：包括看门狗定时器、CRC计算单元、I/O端口等，增加了系统的稳定性和安全性。 STM32ZET6芯片的手册提供了详细的技术规格、电气特性、封装信息、应用电路图和编程指南等内容，是开发基于STM32F103xC、STM32F103xD和STM32F103xE的项目时不可或缺的参考文档。开发者可以通过这份手册深入理解芯片的功能和操作方式，从而充分利用其性能，进行高效且可靠的系统设计。

Description STM32F103xC, STM32F103xD, STM32F103xE

16/144 DocID14611 Rev 12

2.3.6 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.7 Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex

-M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

2.3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

DocID14611 Rev 12 17/144

STM32F103xC, STM32F103xD, STM32F103xE Description

136

2.3.10 Boot modes

At startup, boot pins are used to select one of three boot options:

• Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

2.3.11 Power supply schemes

• V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC

or DAC is used). V

DDA

and V

SSA

must be connected to V

and V

, respectively.

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.13 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop modes.

• Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Description STM32F103xC, STM32F103xD, STM32F103xE

18/144 DocID14611 Rev 12

2.3.14 Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three

low-power modes to achieve the best compromise between low-power consumption, short

startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose, basic

and advanced-control timers TIMx, DAC, I

S, SDIO and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

Description STM32F103xC, STM32F103xD, STM32F103xE

20/144 DocID14611 Rev 12

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase

PWM multiplexed on 6 channels. They have complementary PWM outputs with

programmable inserted dead-times. They can also be seen as a complete general-purpose

timer. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes)

• One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)

embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line

devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler

and feature 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output. This gives up to 16 input captures / output compares / PWMs on the

largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

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