Xilinx LogiCORE IP DDS：高性能直接数字频率合成器

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"直接数字频率合成器(DDS)是一种先进的信号生成技术，相较于传统频率合成器，DDS具备成本效益、低功耗、高分辨率和快速切换频率的特点。DDS由相位生成器和相位到正弦/余弦查找表两部分组成，能够通过AXI4-Stream接口提供高性能优化的波形生成。Xilinx LogiCORE IP DDS Compiler 核心为Virtex-7、Kintex-7、Virtex-6和Spartan-6 FPGA提供了即插即用的解决方案，并支持AXI4-Stream协议。该核心可以单独生成相位发生器或正弦/余弦查找表，也可组合使用，并且可以选择性地添加抖动功能以优化输出性能。" 直接数字频率合成器（DDS）是一种数字信号处理技术，用于生成连续的模拟信号。其工作原理基于数字频率合成的基本概念，即通过改变相位累加器的输入频率来改变输出信号的频率。DDS的核心组件包括： 1. 相位累加器：这是DDS的核心，它将一个固定的频率字（频率控制字）与一个初始相位值相加。每次累加操作后，累加器的输出（相位值）将被转换为角度，进而决定了输出信号的幅度。 2. 相位到幅度转换：相位值被映射到正弦或余弦查找表中，查找表存储了不同相位对应的正弦或余弦值。这样，相位信息就转换成了幅度信息，形成模拟信号的幅度采样。 3. 输出波形重构：通过插值或其他方法，将采样的幅度值连接起来，生成连续的模拟波形。 4. AXI4-Stream接口：这是一种广泛应用于FPGA设计的串行数据传输协议，它提供了高效的接口，使得DDS核心能够与其他系统组件无缝集成。 5. 抖动功能：为了提高输出信号的质量，DDS可以采用抖动技术，通过在相位累加器中引入随机变化，降低谐波失真和改善信号的瞬态响应。 Xilinx的LogiCORE IP DDS Compiler核心为现代FPGA提供了灵活的设计选项，能够适应多种应用需求，如通信系统中的调制解调、雷达信号生成、测试测量设备以及音频和视频处理等。用户可以根据实际需求选择单独的相位发生器或正弦/余弦查找表，或者组合使用，以实现最佳性能和资源利用率。 DDS技术以其高效、灵活和高质量的信号生成能力，在现代电子系统设计中扮演着重要角色。Xilinx的DDS IP核则为工程师提供了强大的工具，帮助他们快速构建满足特定需求的频率合成解决方案。

DS794 March 1, 2011 www.xilinx.com 9

Product Specification

LogiCORE IP DDS Compiler v5.0

Phase Dithered DDS

In the phase truncation DDS architecture shown in Figure 1, the quantizer Q1 introduces a phase error in the phase

slope by discarding the least significant part of the high-precision phase accumulator. The phase error due to the

discarded fractional part of the address count is a periodic series which results in an undesired spectral line

structure. Figure 6 provides an example of this process for a DDS with a table depth N = 1024 and table sample

precision of 16 bits. Figure 6 (a) is the phase error generated by taking the difference between the quantizer input

and output signals, Figure 6 (b) is the output time series and Figure 6 (c) is the signal output spectrum. Observe in

Figure 6 (a) the periodic sawtooth structure of the phase error signal. The line spectrum associated with this

correlated error sequence is impressed on the final output waveform and results in spectral lines in the synthesizer

output spectrum. These spurious components can be clearly seen in Figure 6 (c).

This structure can be suppressed by breaking up the regularity of the address error with an additive randomizing

signal. This randomizing sequence, called dither, is a noise sequence, with variance approximately equal to the least

significant integer bit of the phase accumulator. The dither sequence is added to the high-precision accumulator

output prior to quantization by Q1.

The dithered DDS supplies, approximately, an additional 12 dB of spurious free dynamic range (SFDR) in

comparison to a phase truncation design. This is achieved by spreading the spectral energy of the phase error

signal. The additional logic resources required to implement the dither sequence generator are not significant.

To provide S dB of spur suppression using a phase truncation DDS, as referenced to the 0 dB primary tone, the

internal lookup table must support at least address bits. To achieve this same performance using the

dithered architecture requires two fewer address bits, minimizing the number of block RAMs (or logic slices for a

distributed memory implementation) used in the FPGA implementation. In summary, for a dithered DDS

implementation, the number of address bits needed to support dB spur suppression is equal to .

X-Ref Target - Figure 6

Figure 6: DDS Plots Showing (a) Phase Error Time Series (b) Complex Output Time Series

0 20 40 60 80 100

0.5

(a)

0 20 40 60 80 100

-1

(b)

0 0.1 0.2 0.3 0.4 0.5

-100

-50

FREQUENCY

(c)

S6⁄

–

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