Marvell Alaska 88E系列10/100/1000Mbps高效能以太网收发器规格说明书

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本文档详细介绍了Marvell公司的Alaska系列88E1510、88E1518、88E1512和88E1514集成10/100/1000 Mbps节能以太网收发器的数据手册。这些产品专为在能源效率方面提供卓越性能而设计，适用于10Base-T、100Base-TX和1000Base-T（千兆以太网）的应用场景。88E1512型号特别提到了56引脚QFN封装，这种小型封装有助于减小系统尺寸和功耗。 1.1.2节详细列出了88E1512的具体引脚布局，这对于电路板设计者来说至关重要，它确保了正确连接电源、数据信号线和其他控制信号，以便实现高速、可靠的通信。这款芯片旨在满足现代网络设备对低功耗和高效能的需求，通过采用节能技术降低电力消耗，从而节省运行成本并减少对环境的影响。文档还指出，这份资料是公开版本，适用于一般信息查询，但包含的信息可能具有特殊重要性。在使用过程中，用户应遵循警告和注意事项，如避免潜在硬件损坏或数据丢失，以及个人伤害的风险。Marvell公司保留随时更新文档的权利，并强调本资料未经许可不得复制或传播，且不承担因使用文档中的信息导致的任何责任，包括但不限于商品质量保证或特定用途的适用性。此外，文档的免责声明表明，Marvell不对文档内容的准确性或完整性做出任何保证，用户在依赖这些信息时应自行判断其适用性。欲获取更多信息或支持，请访问Marvell的官方网站<http://www.marvell.com>。本数据手册提供了关于Alaska系列88E1510/88E1518/88E1512/88E1514以太网收发器的技术细节，是网络设备制造商、工程师和系统集成者进行产品设计和评估的重要参考资源。

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 16 Document Classification: Public February 23, 2018

Figure 34: MDC/MDIO Timing ........................................................................................................................138

Figure 35: ........................................................................................................................................................139

Figure 36: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing ........................................................140

Figure 37: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................141

Figure 38: 10/100/1000BASE-T to SGMII Latency Timing ..............................................................................142

Figure 39: SGMII to 10/100/1000BASE-T Latency Timing ..............................................................................142

5 Package Mechanical Dimensions .................................................................................................143

Figure 40: 88E1510/88E1518 48-pin QFN Package Mechanical Drawings ....................................................143

Figure 41: 88E1512/88E1514 56-pin QFN Package Mechanical Drawings ....................................................145

6 Part Order Numbering/Package Marking......................................................................................147

Figure 42: Sample Part Number ......................................................................................................................147

Figure 43: 88E1510 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................149

Figure 44: 88E1518 48-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 45: 88E1512 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................150

Figure 46: 88E1514 56-pin QFN Commercial Package Marking and Pin 1 Location ......................................151

Figure 47: 88E1510 48-pin QFN Industrial Package Marking and Pin 1 Location...........................................151

Figure 48: 88E1512 56-pin QFN Industrial Package Marking and Pin 1 Location...........................................152

A Revision History .............................................................................................................................153

Alaska 88E1510/88E1518/88E1512/88E1514

Datasheet - Public

Page 20 Document Classification: Public February 23, 2018

The RGMII supports 10/100/1000BASE-T modes of operation.

Table 4: RGMII

48-QFN

Pin #

Pin Name Pin

Type

Description

47 TX_CLK I RGMII Transmit Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance depending on speed.

2 TX_CTRL I RGMII Transmit Control. TX_EN is presented on the rising edge of TX_CLK.

A logical derivative of TX_EN and TX_ER is presented on the falling edge of

TX_CLK.

TXD[3]

TXD[2]

TXD[1]

TXD[0]

I RGMII Transmit Data.

TXD[3:0] run at double data rate with bits [3:0] of each byte to be transmitted

on the rising edge of TX_CLK, and bits [7:4] presented on the falling edge of

TX_CLK.

In 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on

the rising edge of TX_CLK.

40 RX_CLK O RGMII Receive Clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference

clock with ± 50 ppm tolerance derived from the received data stream

depending on speed.

37 RX_CTRL O RGMII Receive Control. RX_DV is presented on the rising edge of RX_CLK.

A logical derivative of RX_DV and RX_ER is presented on the falling edge of

RX_CLK.

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O RGMII Receive Data. RXD[3:0] run at double data rate with bits [3:0] of each

byte received on the rising edge of RX_CLK, and bits [7:4] presented on the

falling edge of RX_CLK.

In 10/100BASE-T modes, the receive data nibble is presented on RXD[3:0] on

the rising edge of RX_CLK.

Table 5: Management Interface and Interrupt

48-QFN

Pin #

Pin Name Pin

Type

Description

4 MDC I MDC is the management data clock reference for the serial management

interface. A continuous clock stream is not expected. The maximum frequency

supported is 12 MHz.

5 MDIO I/O MDIO is the management data. MDIO transfers management data in and out of

the device synchronously to MDC. This pin requires a pull-up resistor in a

range from 1.5 kΩ to 10 kΩ.

Table 6: LED Interface

48-QFN

Pin #

Pin Name Pin

Type

Description

10 LED[0] O LED output.

9 LED[1] I/O LED output

8 LED[2]/INTn O LED/Interrupt outputs.

LED[2] pin also functions as an active low interrupt pin.

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