Chapter 1. Introduction
This specification describes the RISC-V Supervisor Binary Interface, known from here on as SBI. The
SBI allows supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V
implementations by defining an abstraction for platform (or hypervisor) specific functionality. The
design of the SBI follows the general RISC-V philosophy of having a small core along with a set of
optional modular extensions.
SBI extensions as whole are optional but they shall not be partially implemented. If
sbi_probe_extension() signals that an extension is available, all functions present in the SBI version
reported by sbi_get_spec_version() must conform to that version of the SBI specification.
The higher privilege software providing SBI interface to the supervisor-mode software is referred as an
SBI implementation or Supervisor Execution Environment (SEE). An SBI implementation (or SEE)
can be platform runtime firmware executing in machine-mode (M-mode) (see below Figure 1) or it can
be some hypervisor executing in hypervisor-mode (HS-mode) (see below Figure 2).
Figure 1. RISC-V System without H-extension
Figure 2. RISC-V System with H-extension
The SBI specification doesn’t specify any method for hardware discovery. The supervisor software
must rely on the other industry standard hardware discovery methods (i.e. Device Tree or ACPI) for
Chapter 1. Introduction | Page 5
RISC-V Supervisor Binary Interface Specification | © RISC-V