Hindawi Publishing Corporation
e Scientic World Journal
Volume , Article ID , pages
http://dx.doi.org/.//
Research Article
Parallel PWMs Based Fully Digital Transmitter with Wide
Carrier Frequency Range
Bo Zhou, Kun Zhang, Wenbiao Zhou, Yanjun Zhang, and Dake Liu
School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
Correspondence should be addressed to Bo Zhou; zhoubo@bit.edu.cn
Received July ; Accepted August
Academic Editors: A. Garcia-Zambrana and A. Jugessur
Copyright © Bo Zhou et al. is is an open access article distributed under the Creative Commons Attribution License, which
permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
e carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed,
where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM
and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in nm CMOS for high
reconguration. e proposed architecture achieves wide CF range of M– GHz, high power eciency of %, and low error
vector magnitude (EVM) of %, with spectrum purity of dB optimized in comparison to the existing designs.
1. Introduction
Wireless communication is becoming more and more impor-
tant and ubiquitous in modern society. To support numbers
of communication standards in small and same handheld
devices, there are growing demands for exible transmit-
ters and receivers supporting multimode communications
with high eciency. Recently, lots of researches have been
conducted in RF recongurable transceivers using novel
hardware implementation. is paper focuses on fully digital
wireless transmitters.
e existing design [, ], employing all-digital phase-
locked loop (ADPLL) and delta-sigma modulator, intro-
duces large fractional spurs and requires strict energy match
between power branches. e existing transmitters with
quadrature [, ] or delay-line [, ] based intermediate-
frequency (IF) pulse-width modulation (PWM), are not apt
for low carrier-frequency (CF) applications, under which the
band-pass lter (BPF) fails to suppress IF component or
harmonics closer to the carrier. e existing radio-frequency
(RF) PWM [] or direct digital frequency synthesizer (DDFS)
[] based transmitters, aiming for low CF conditions, are not
considered as fully digital designs, since analogue feedback or
mixed-signal congurations are used. e existing architec-
ture [] employing outphasing amplication technique is not
widely used in commerce due to strict matching requirements
between dual paths and distortion and eciency degradation
caused by RF power combiner.
In this paper, delay-line based CF-PWM with precor-
rection logic is proposed, where the only carrier clock is
employed to ensure spectrum purity under low CF con-
ditions. By combining IF-PWM for high CF and precor-
rected CF-PWM for low CF, a fully digital transmitter is
presented with wide CF range and high eciency. A unit-
delay autocalibration loop for delay lines is also proposed
with recongurable carrier frequency
𝐶
.
2. Architecture
Figure shows the proposed fully digital transmitter with
parallel IF- and CF-PWMs. e coordinate rotation digital
computer (CORDIC) algorithm accomplishes the conversion
from / to polar coordinate /Φ []. e wide CF range
of M– GHz is divided into low
𝐶
band of M– MHz
and high
𝐶
band of M– GHz. About MHz frequency
overlapareaischosentoavoidtheswitchingjitterbetween
high and low
𝐶
bands. Under low CF band, the transmitter
workinginmode“”andCF-PWMenabling,multibitphase
component Φis mapped to /-period position of the carrier
clock,andmultibitenvelopecomponent is converted to
precorrected pulse width of the carrier clock. For high CF
case,mode“”andIF-PWMenabling,phaseΦ is conveyed