Xilinx FPGA 设计指南：RAM与FIFO Core应用

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“Xilinx Synthesis and Verification Design Guide2.pdf”是一份针对Xilinx FPGA设计的综合与验证技术指南，涵盖了如何使用RAM、FIFO Core等关键组件。在Xilinx FPGA设计中，综合（Synthesis）和验证（Verification）是两个至关重要的步骤。综合过程将高级语言描述的设计（如Verilog或VHDL）转换成硬件描述语言（HDL），这些语言可以直接映射到FPGA的逻辑资源。这个过程涉及到逻辑优化、时序分析和约束处理，以确保设计能够在目标FPGA上高效运行。本指南可能详细介绍了如何有效地使用Xilinx工具进行综合。这通常包括设置约束文件，如时钟速度和功耗目标，以及理解综合报告，这些报告提供了关于设计性能和资源利用率的关键信息。综合策略，如逻辑划分、资源共享和逻辑重用，也可能在指南中有深入探讨。验证则是确保设计按预期工作的过程。这包括模拟（Simulation）和形式验证（Formal Verification）。在Xilinx的8.1i版本设计环境中，用户可能学习如何使用仿真工具来验证设计在不同条件下的行为，检查模块间的接口是否正确，以及功能是否符合规范。此外，指导可能还涵盖如何使用覆盖率工具来度量和确认验证的完整性。特别地，对于RAM和FIFO Core的使用，这份指南会讲解如何在FPGA设计中集成这些存储元素。RAM常用于实现数据缓冲和存储，而FIFO（先进先出）Core则用于处理数据流的同步问题，尤其是在处理高速数据传输时。设计者可能需要了解如何配置这些IP核的大小、读写端口数量、深度以及接口协议，以满足特定应用的需求。在使用这份文档时，用户需要注意知识产权的问题。Xilinx提供了这份设计指南供开发者用于开发与Xilinx FPGA兼容的设计，但不允许未经授权的复制、分发或展示。此外，Xilinx不承担因应用或使用设计导致的任何责任，并且不提供任何专利、版权或其他权利的许可。设计者有责任获取实施设计所需的任何额外许可。最后，Xilinx保留随时根据需要更新或修改设计的权利，以保持其设计的最新性和最佳性能。这意味着设计者需要定期查阅最新的设计指南以保持他们的知识是最新的。

16 www.xilinx.com Synthesis and Simulation Design Guide

8.1i

RTL Simulation Using Xilinx Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Simulating Certain Xilinx Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

CLKDLL, DCM and DCM_ADV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

CLKDLL/DCM Clocks Do Not Appear De-Skewed . . . . . . . . . . . . . . . . . . . . . . . . . . 267

TRACE/Simulation Model Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Non-LVTTL Input Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Viewer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Attributes for Simulation and Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Simulating the DCM in Digital Frequency Synthesis Mode Only. . . . . . . . . . . . . . . . . 269

JTAG / BSCAN (Boundary Scan) Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Glitches in Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Debugging Timing Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Identifying Timing Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Verilog System Timing Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

VITAL Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Timing Problem Root Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Design Not Constrained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Path Not or Improperly Constrained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Design Does Not Meet Timespec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Simulation Clock Does Not Meet Timespec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Unaccounted Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Asynchronous Inputs, Asynchronous Clock Domains, Crossing Out-of-Phase . . . . . . 275

Debugging Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Special Considerations for Setup and Hold Violations . . . . . . . . . . . . . . . . . . . . . . . . 276

Zero Hold Time Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Negative Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

RAM Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

$Width Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

$Recovery Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

ModelSim SE/PE/XE VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

VCS-MX VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

NC-SIM VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

NC-SIM Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Using Library Source Files With Compile Time Options . . . . . . . . . . . . . . . . . . . . . . . 280

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

VCS-MX Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Using Library Source Files With Compile Time Options . . . . . . . . . . . . . . . . . . . . . . . 281

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

ModelSim Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Using Library Source Files With Compile Time Options . . . . . . . . . . . . . . . . . . . . . . . 283

Using Shared Precompiled Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

IBIS I/O Buffer Information Specification (IBIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Chapter 7: Equivalency Checking

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Chapter 1: Introduction

Understanding FPGA architecture allows you to create HDL code that effectively uses

FPGA system features. To learn more about designing FPGA devices with HDL:

• Enroll in training classes offered by Xilinx and by the vendors of synthesis software.

• Review the sample HDL designs in the later chapters of this guide.

• Download design examples from Xilinx Support

• Take advantage of the many other resources offered by Xilinx, including

documentation, tutorials, Tech Tips

, service packs, a telephone hotline, and an

answers database. See “Additional Resources” in the Preface of this guide.

Advantages of Using HDLs to Design FPGA Devices

Using HDLs to design high-density FPGA devices has the following advantages:

• “Top-Down Approach for Large Projects”

• “Functional Simulation Early in the Design Flow”

• “Synthesis of HDL Code to Gates”

• “Early Testing of Various Design Implementations”

• “Reuse of RTL Code”

Top-Down Approach for Large Projects

Designers use to create complex designs. The top-down approach to system design

supported by HDLs is advantageous for large projects that require many designers

working together. After they determine the overall design plan, designers can work

independently on separate sections of the code.

Functional Simulation Early in the Design Flow

You can verify the functionality of your design early in the design flow by simulating the

HDL description. Testing your design decisions before the design is implemented at the

RTL or gate level allows you to make any necessary changes early in the design process.

Synthesis of HDL Code to Gates

You can synthesize your hardware description to target the FPGA implementation. This

step:

• Decreases design time by allowing a higher-level specification of the design rather

than specifying the design from the FPGA base elements.

• Generally reduces the number of errors that can occur during a manual translation of

a hardware description to a schematic design.

• Allows you to apply the automation techniques used by the synthesis tool (such as

machine encoding styles and automatic I/O insertion) during the optimization of

your design to the original HDL code. This results in greater optimization and

efficiency.

Early Testing of Various Design Implementations

HDLs allow you to test different implementations of your design early in the design flow.

Use the synthesis tool to perform the logic synthesis and optimization into gates.

Synthesis and Simulation Design Guide www.xilinx.com 19

8.1i

Designing FPGA Devices with HDLs

Additionally, Xilinx FPGA devices allow you to implement your design at your computer.

Since the synthesis time is short, you have more time to explore different architectural

possibilities at the Register Transfer Level (RTL). You can reprogram Xilinx FPGA devices

to test several implementations of your design.

Reuse of RTL Code

You can retarget RTL code to new FPGA architectures with a minimum of recoding.

Designing FPGA Devices with HDLs

If you are used to schematic design entry, you may find it difficult at first to create HDL

designs. You must make the transition from graphical concepts, such as block diagrams,

state machines, flow diagrams, and truth tables, to abstract representations of design

components. Ease this transition by not losing sight of your overall design plan as you

code in HDL.

To effectively use an HDL, you must understand:

• the syntax of the language

• the synthesis and simulator software

• the architecture of your target device

• the implementation tools

This section gives you some design hints to help you create FPGA devices with HDLs.

Designing FPGA Devices with Verilog

Verilog is popular for synthesis designs because:

• Verilog is less verbose than traditional VHDL.

• Verilog is standardized as IEEE-STD-1364-95 and IEEE-STD-1364-2001.

Since Verilog was not originally intended as an input to synthesis, many Verilog constructs

are not supported by synthesis software. The Verilog examples in this guide were tested

and synthesized with current, commonly-used FPGA synthesis software. The coding

strategies presented in the remaining chapters of this guide can help you create HDL

descriptions that can be synthesized.

SystemVerilog is a new emerging standard for both synthesis and simulation. It is

currently unknown if, or when, this standard will be adopted and supported by the

various design tools.

Whether or not you plan to use this new standard, Xilinx recommends that you:

• Review the standard to make sure that your current Verilog code can be readily

carried forward as the new standard evolves.

• Review any new keywords specified by the standard.

• Avoid using the new keywords in your current Verilog code.

Designing FPGA Devices with VHDL

VHSIC Hardware Description Language (VHDL) is a hardware description language for

designing Integrated Circuits (ICs). It was not originally intended as an input to synthesis,

and many VHDL constructs are not supported by synthesis software. However, the high

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Chapter 1: Introduction

level of abstraction of VHDL makes it easy to describe the system-level components and

test benches that are not synthesized. In addition, the various synthesis tools use different

subsets of the VHDL language. The examples in this guide work with most commonly

used FPGA synthesis software. The coding strategies presented in the remaining chapters

of this guide can help you create HDL descriptions that can be synthesized.

Designing FPGA Devices with Synthesis Tools

Most of the commonly-used FPGA synthesis tools have special optimization algorithms

for Xilinx FPGA devices. Constraints and compiling options perform differently

depending on the target device. Some commands and constraints in ASIC synthesis tools

do not apply to FPGA devices. If you use them, they may adversely impact your results.

You should understand how your synthesis tool processes designs before you create FPGA

designs. Most FPGA synthesis vendors include information in their guides specifically for

Xilinx FPGA devices.

Using FPGA System Features

To improve device performance, area utilization, and power characteristics, create HDL

code that uses such FPGA system features as DCM, multipliers, shift registers, and

memory. For a description of these and other features, see the FPGA data sheet

and user

guide. The choice of the size (width and depth) and functional characteristics need to be

taken into account by understanding the target FPGA resources and making the proper

system choices to best target the underlying architecture.

Designing Hierarchy

Hardware Description Languages (HDLs) give added flexibility in describing the design.

However, not all HDL code is optimized the same. How and where the functionality is

described can have dramatic effects on end optimization. For example:

• Certain techniques may unnecessarily increase the design size and power while

decreasing performance.

• Other techniques can result in more optimal designs in terms of any or all of those

same metrics.

This guide will help instruct you in techniques for optional FPGA design methodologies.

Design hierarchy is important in both the implementation of an FPGA and during

incremental or interactive changes. Some synthesizers maintain the hierarchical

boundaries unless you group modules together. Modules should have registered outputs

so their boundaries are not an impediment to optimization. Otherwise, modules should be

as large as possible within the limitations of your synthesis tool.

The “5,000 gates per module” rule is no longer valid, and can interfere with optimization.

Check with your synthesis vendor for the preferred module size. As a last resort, use the

grouping commands of your synthesizer, if available. The size and content of the modules

influence synthesis results and design implementation. This guide describes how to create

effective design hierarchy.

Specifying Speed Requirements

To meet timing requirements, you should understand how to set timing constraints in both

the synthesis tool and the placement and routing tool. If you specify the desired timing at

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