The receiver uses three stages of
downconversion to provide analogue baseband
quadrature outputs. Analogue to Digital
Converters (ADCs) convert the baseband
outputs to digital and the baseband processor
carries out timing synchronisation,
equalisation and error correction. An
alternative topology to baseband sampling is
to sample an IF signal directly. In this case the
final mix to baseband is performed digitally.
This is often achieved by “sub-sampling”,
which allows the sampling rate to be below the
IF frequency [5]. One disadvantage with this
technique is that the ADC must work at a
higher frequency making it more difficult to
achieve the required performance.
The main disadvantage with a baseband
sampling approach, as used in this design, is
DC offset signals caused by leakage of the LO
signal used for the mix to baseband. Any LO
signal leaking into the IF circuits is mixed
down to zero frequency giving a DC offset. A
common way of significantly reducing this
problem is to generate the IF LO signal at a
multiple of the required frequency and to
divide it down on-chip. A divide by 2
approach can also be used as a means of
generating accurate quadrature LO signals.
The signal drives two dividers with the flip-
flops in the dividers being triggered on either
the negative or positive edges, to give output
signals at half the input frequency with 90° of
phase difference.
A treble conversion superhet design is a
popular receive architecture for GSM
handsets. It allows a first IF at a high enough
frequency (in this case 225MHz) to allow good
filtering of the image signal. A second
conversion to a lower IF allows the AGC to be
realised at a lower frequency, with a final
conversion to baseband or to a third IF in the
case of IF sampling designs. Double
conversion architectures are also possible but
the AGC must then be realised at a higher
frequency. Another alternative, which is
possible, is to use a direct conversion to
baseband architecture [8]. This is attractive
because it reduces the number of RF
components used and removes the need for
image filtering. However, the practical
difficulties of implementing a direct
conversion GSM receiver should not be
underestimated [5].
In transmit mode the inputs to the transceiver
IC are differential I and Q baseband signals.
These are used to modulate a relatively low
frequency IF signal, which is then used to
modulate a VCO operating at the transmit
frequency in a translational loop architecture.
The translational loop works by mixing the
transmit VCO signal with the channel
oscillator to generate an IF signal. A phase
comparator is used to compare this IF to the
modulated IF with the difference being passed
back to the transmit VCO, via a loop filter, as
an error signal. This closes a phase locked
loop around the transmit VCO which locks it
to the modulated IF signal. Translational loop
architectures are only possible with constant
envelope modulation schemes such as
Gaussian Minimum Shift Keying (GMSK).
One disadvantage with a translational loop
architecture is that an extra VCO is required
as compared to a direct modulation or
superhet. architecture. However, it has become
increasingly popular for the following reasons:
• The input to the PA is not the direct output
of a mixer with all of it’s associated
spurious mixing products. This eases the
filtering requirements of the transmitter.
• The oscillator driving the PA can have a
relatively high output level. Less PA gain
is therefore required, which reduces the
thermal noise generated at the output of
the PA, making it easier to pass the receive
band noise emissions requirement. This
means a switch can be used at the antenna
port instead of a diplexer filter, which is
more expensive and has higher loss.
• Susceptibility to pulling of the transmit
VCO is reduced because the wide loop
bandwidth makes it very agile and able to
track and correct any sudden pulling
effects
Synthesiser Design and
Measured Performance
Three synthesiser designs are used in the
handset: a channel VCO that must select
frequencies from 1705.2MHz to 1774.8MHz
in 200kHz steps. An IF VCO which is set to
540MHz and the translational loop oscillator
which must tune over the transmit band from
1850.2MHz to 1909.8MHz [9]. The
synthesiser for the translational loop is on the
transceiver IC, the other two oscillators make
use a single dual synthesiser IC. VCO
modules were used for the channel and