Semiconductor Components Industries, LLC, 2003
February, 2003 - Rev. 2
1 Publication Order Number:
AND8106/D
AND8106/D
100 Watt, Universal Input,
PFC Converter
ON Semiconductor
General Description
This 100 watt converter demonstrates the wide range of
features found on the NCP1650. This chip is capable of
controlling PFC converters well into the kilowatt range.
In addition to excellent power factor, this chip offers fixed
frequency operation in continuous and discontinuous modes
of operation. It has a wide variety of protection features,
including instantaneous current limiting, average current
limiting, and true power limiting.
This unit will provide 400 V of well regulated power from
an input source with a frequency range from 50 Hz to 60 Hz,
and a voltage range of 85
V
rms
to 265
V
rms
. It is fully self
contained and includes a high voltage start-up circuit, and
bias supply that operates off of the boost inductor.
Features
• Fixed Frequency Operation
• Shutdown Circuit
• Operation Over the Universal Input Range
• Multiple Protection Schemes
• True Power Limiting
• Start-Up and Bias Circuits Included
Circuit Description
Start-Up Circuit
The start-up circuit allows the unit to use power from the
input line to begin operation, and then shuts down to allow
operation off of the bias winding, which reduces losses in the
circuit.
The start-up circuit has three modes of operation. One is
used for starting the NCP1650 when the chip is functional,
one is for bias power during shutdown operation, and the
third is the off state.
When power is initially applied to the unit, the gate of the
pass transistor will be high, and the FET will be fully
enhanced. The current into the V
CC
capacitance at pin 1 will
be limited by the three 10 k resistors in series with the FET.
Figure 1. Start-Up Circuit Schematic
FQP1N60
10 k 10 k 10 k
V
out
1.2 M
MMSZ5248BT1
1 F
V
bias
V
in
1
NCP1650
This circuit will provide current as long as the FET is
enhanced. For this to occur, the gate to source voltage must
be greater than the gate threshold voltage. For this device
that value is nominally, 4.0 V. The zener breakdown voltage
is 18 V, so the FET will turn off at:
Vchg
max
18 V 4.0 V 14 Volts
As the output capacitor is charged up during the turn-on
sequence, the bias supply voltage will also increase until the
source of the FET exceeds 14 V. At this point, the FET will
cease conduction, and all of the V
CC
power will be supplied
via the bias circuit from the power inductor.
If the unit is commanded into the shutdown mode, the chip
will reduce its bias current to 0.5 mA and the start-up circuit
will then maintain a regulated voltage of approximately
14 V on the V
CC
pin until the device becomes operational.
APPLICATION NOTE
http://onsemi.com