TI AFE5816：16通道超声波AFE，低功耗与高精度

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TI-AFE5816是一款高性能的模拟前端(AFE)芯片，专为超声波应用设计，具备16通道功能，可扩展至32通道，提供全面的信号处理能力。其核心特性包括： 1. **低功耗与高精度**：AFE5816拥有极低的通道功耗，单通道达到90mW，同时具备出色的噪声性能，1-nV/√Hz的噪声水平确保了信号的纯净度。在不同采样率下，如65MSPS和80MSPS，ADC的分辨率分别为14位和12位，分别对应着优异的信噪比(SNR)，65MSPS下为75dBFS，80MSPS下为72dBFS。 2. **信号链优化**：AFE5816的信号链经过精心设计，支持时间增益补偿(TGC)和连续波(CW)模式，以适应多种应用场景的需求。此外，还配备了数字时间增益补偿(DTGC)功能，提供了6dB至45dB的总增益范围，线性输入范围为1VPP。 3. **输入模块**：内置输入衰减器和低噪声放大器(LNA)支持DTGC功能，衰减范围从0dB到8dB（步进0.125dB），并兼容50Ω至800Ω的源阻抗。LNA的增益范围宽广，从14dB到45dB，具有极低的输入电流噪声，仅为1.2pA/√Hz。 4. **滤波器和接口**：集成三阶线性相位低通滤波器，频率选项包括10MHz、15MHz、20MHz和25MHz。ADC采用可编程分辨率设计，不仅支持高速数据传输，最高可达1GBPS，还优化了功耗和噪声性能。 5. **电源效率与散热设计**：AFE5816在噪声和功耗方面表现出色，例如在65MSPS的TGC模式下，每通道仅消耗90mW，且噪声水平极低，达到1nV/√Hz。 TI-AFE5816是一款功能强大的超声波信号处理平台，适用于对噪声、动态范围和功耗要求严格的系统设计，如医疗成像、工业检测和物联网应用。其集成化的设计减少了外部组件的需求，提高了系统的稳定性和可靠性。

AFE5816

ZHCSDT7E –APRIL 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

(1) NF is measured as the SNR at the output of the device relative to the SNR at the input resulting from ths noise of source resistance R

(2) Designing the power supply with 2X of the typical current capacity is recommended to take care of current variation across devices,

switching current, signal current, and so forth.

8.6 Electrical Characteristics: CW Mode

At T

= 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 =

1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied

with source resistance R

= 50 Ω at frequency f

= 2 MHz, CW_CLK1X = 2-MHz differential clock, and CW_CLK_NX = 32-

MHz differential clock. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode and ADC in

power-down mode. Minimum and maximum values are specified across the full temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

GENERAL

MAX, CW

Maximum input swing 300 mV

V2I

Voltage-to-current resistor

at LNA output

500 Ω

OPP

Peak-to-peak output

current per channel

4.8 mA/Ch

N,IRCW

Input voltage noise

1 channel 1.55

nV/√Hz

16 channels 0.45

N,ORCW

Output current noise

1 channel 19

pA/√Hz

16 channels 80

Noise figure

(1)

= 100 Ω, 1 channel 4

= 100 Ω, 16 channels 4.8

CWM

CW mixer conversion loss 4 dB

1 kHz,CW

Phase noise

16X CW clock mode, calculated at

1-kHz frequency

Signal to 1 channel –151

dBc/Hz

Signal to 16 channels –161

IMD3

Two-tone, third-order

intermodulation distortion

IN1

= 5 MHz, f

IN2

= 5.01 MHz, both tones at –6-dBFS

amplitude,

input to all the 16 channels.

–60

dBc

IN1

= 5 MHz, f

IN2

= 5.01 MHz, both tones at –6-dBFS

amplitude, input to single channel

–70

IQG

I/Q channel gain matching

16X and 8X CW clock mode ±0.06

4X CW clock mode ±0.08

IQP

I/Q channel phase

matching

16X and 8X CW clock mode ±0.05

Degrees

4X CW clock mode ±0.15

REJ

Image rejection ratio

16X and 8X CW clock mode –49

dBc

4X CW clock mode –46

LNACW

LNA gain in CW mode 18 dB

HPF

High-pass filter

–1-dB cutoff frequency across LNA_HPF_PROG register

settings; see register 199

kHz

150

300

600

POWER DISSIPATION

CW/Ch

Power dissipation

per channel (CW mode)

CW mode, CW_CLK1X = 5 MHz,

CW_CLK_NX = 80 MHz

No signal 60

mW/Ch

300-mV

input signal

to all 16 channels

A_1P9

AVDD_1P9 current

(1.9 V)

(2)

CW mode, CW_CLK1X = 5 MHz,

CW_CLK_NX = 80 MHz

No signal 385

300-mV

input signal

to all 16 channels

450

A_3P15

AVDD_3P15 current

(2)

CW mode, CW_CLK1X = 5 MHz,

CW_CLK_NX = 80 MHz

No signal 70

300-mV

input signal

to all 16 channels

AFE5816

www.ti.com.cn

ZHCSDT7E –APRIL 2015–REVISED SEPTEMBER 2017

Electrical Characteristics: CW Mode (continued)

At T

= 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 =

1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied

with source resistance R

= 50 Ω at frequency f

= 2 MHz, CW_CLK1X = 2-MHz differential clock, and CW_CLK_NX = 32-

MHz differential clock. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode and ADC in

power-down mode. Minimum and maximum values are specified across the full temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC PERFORMANCE (Power)

PSRR

1 kHz

AC power-supply rejection

ratio: tone at output

relative to tone on supply

100 mV

, 1-kHz tone on supply

AVDD_1P9 –60

dBc

AVDD_3P15 –75

PSMR

1 kHz

AC power-supply

modulation ratio:

intermodulation tone at

output resulting from tones

at supply and input

measured relative to input

tone

100 mV

, 1-kHz tone on supply

and –1-dBFS, 5-MHz tone at input

AVDD_1P9 –50

dBc

AVDD_3P15 –50

(1) All digital specifications are characterized across operating temperature range but are not tested at production.

(2) When SDOUT operation is performed in VCA die, typical output voltage of SDOUT is 1.9 V.

8.7 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. Typical values are at T

= 25°C, minimum and maximum values are across the full temperature range of T

MIN

–40°C to T

MAX

= 85°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, DVDD_1P8 =

1.8 V, external differential load resistance between the LVDS output pair, and R

LOAD

= 100 Ω, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS

(PDN_FAST, PDN_GBL, RESET, SCLK, SDIN, SEN, TGC_PROF<1>, TGC_PROF<2>, TGC_SLOPE, TGC_UP_DN, TR_EN<1>,

TR_EN<2>, TR_EN<3>, TR_EN<4>, TX_TRIG)

(1)

High-level input voltage

0.75 × max [AVDD_

1P9, DVDD_1P8]

Low-level input voltage

0.25 × min [AVDD_

1P9, DVDD_1P8]

High-level input current 150 µA

Low-level input current 150 µA

Input capacitance 8 pF

DIGITAL OUTPUTS (SDOUT)

(1)

High-level output voltage 1.6 1.8

(2)

Low-level output voltage 0 0.2 V

Output impedance 50 Ω

LVDS DIGITAL OUTPUTS (DOUT)

(1)

| Output differential voltage

100-Ω external load connected differentially

across DOUT

320 400 480 mV

Output offset voltage

(common-mode voltage of

DOUTP

and DOUTM

)

100-Ω external load connected differentially

across DOUT

0.9 1.03 1.15 V

AFE5816

ZHCSDT7E –APRIL 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

(1) See Figure 1.

(2) All LVDS specifications are characterized but are not tested at production.

(3) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be

a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across

channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example,

the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.

(4) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock.

(5) t

is the ADC clock period in nanoseconds (ns).

8.8 Output Interface Timing Requirements

Typical values are at T

= 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V,

DVDD_1P8 = 1.8 V, differential ADC clock, LVDS load C

LOAD

= 5 pF, R

LOAD

= 100 Ω, 14-bit ADC resolution, and sample rate

= 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of T

MIN

= –40°C to

MAX

= 85°C.

MIN TYP MAX UNIT

GENERAL

Aperture delay

(1)

1.6 ns

δt

Aperture delay variation from device to device

(at same temperature and supply)

±0.5 ns

APJ

Aperture jitter with LVPECL clock as input clock 0.5 ps

ADC TIMING

ADC latency

Default after reset

(1)

8.5

ADC clocks

Low-latency mode 4.5

LVDS TIMING

(2)

Frame clock frequency

(1)

CLKIN

MHz

FRAME

Frame clock duty cycle 50%

SER

Number of bits serialization of each ADC word 12 16 Bits

Output rate of serialized data

1X output data rate

mode

SER

× f

CLKIN

1000

Mbps

2X output data rate

mode

2 × N

SER

× f

CLKIN

1000

Bit clock frequency f

/ 2 500 MHz

BIT

Bit clock duty cycle 50%

Data bit duration

(1)

1 1000 / f

PDI

Clock propagation delay

(1)

6 × t

+ 5 ns

δt

PROP

Clock propagation delay variation from device to device

(at same temperature and supply)

±2 ns

ORF

DOUT, DCLK, FCLK rise and fall time, transition time

between –100 mV and +100 mV

0.2 ns

OSU

Minimum serial data, serial clock setup time

(1)

/ 2 – 0.4 ns

Minimum serial data, serial clock hold time

(1)

/ 2 – 0.4 ns

Minimum data valid window

(3)(1)

– 0.65 ns

TX_TRIG TIMING

TX_TRIG_DEL

Delay between TX_TRIG and TX_TRIGD

(4)

0.5 0.4 × t

(5)

SU_TX_TRIGD

Setup time related to latching TX_TRIG relative to the

rising edge of the system clock

0.6 ns

H_TX_TRIGD

Hold time related to latching TX_TRIG relative to the

rising edge of the system clock

0.4 ns

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