Lattice FPGA DDR3控制器用户指南

需积分: 10 44 浏览量更新于2024-07-17 收藏 4.74MB PDF 举报

"本文档是Lattice Semiconductor公司关于Double Data Rate (DDR3) SDRAM Controller IP Core的用户指南，详细介绍了如何在Lattice FPGA中实现DDR3内存的读写控制。作者通过实践验证，该方法已在板卡上成功运行。" DDR3 SDRAM Controller IP Core是Lattice FPGA设计中用于高效管理DDR3内存模块的关键组件。这个IP核提供了一套完整的解决方案，涵盖了DDR3内存控制器的所有功能，包括命令解码、命令应用、片上终结(On-Die Termination, ODT)、初始化、写入校准、读取训练以及模式寄存器编程等。 1. **快速事实(Quick Facts)**：这部分可能包含有关DDR3 SDRAM Controller IP Core的一些关键特性或性能指标，但具体内容未在摘要中给出。 2. **功能描述(Functional Description)**： - **概述(Overview)**：概述了IP核在FPGA中的作用，如何与DDR3内存颗粒进行通信，以及其在系统中的位置。 - **DDR3 MC Module**（Memory Controller）：这是IP核的核心部分，负责管理和协调所有与DDR3内存的交互。 - **命令解码逻辑(Command Decode Logic)**：这部分解析来自FPGA的内存访问请求，并转换成DDR3内存可以理解的命令。 - **命令应用逻辑(Command Application Logic)**：将解码后的命令正确地应用到DDR3内存总线上。 - **片上终结(On-Die Termination, ODT)**：是DDR3内存的一种特性，用于减少信号反射，提高信号质量。 - **DDR3 PHY Module**：物理层模块，处理与DDR3内存颗粒的物理接口，包括数据路径逻辑和信号描述。 - **初始化模块(Initialization Module)**：负责设置DDR3内存的初始状态，如时钟调整、模式寄存器配置等。 - **写入校准(Write Leveling)**：确保数据在写入内存时与内存的时钟同步。 - **读取训练(Read Training)**：仅适用于ECP5设备，用于优化读取数据的准确性。 - **选择READ_PULSE_TAP值(Selecting READ_PULSE_TAP Value)**：仅适用于Lattice ECP3设备，是读取训练的一部分，调整读取脉冲以提高读取性能。 - **数据路径逻辑(Data Path Logic)**：处理数据的传输，包括读取和写入操作。 3. **用户界面(Using the Local User Interface)**：用户可以通过本地接口设置和控制DDR3控制器，如初始化控制、命令和地址映射等。 4. **初始化控制(Initialization Control)**：在开始使用DDR3内存之前，需要进行必要的初始化设置，如时钟设置、模式寄存器编程等。 5. **命令和地址(Command and Address)**：IP核支持用户定义的内存访问命令，如标准的WRITE、WRITEA、READ、READA命令。 6. **用户命令(User Commands)**： - **WRITE**：执行向DDR3内存写入数据的操作。 - **WRITEA**：可能是带附加信息的写命令。 - **READ**：从DDR3内存读取数据。 - **READA**：可能是指带有附加信息的读命令。 7. **刷新支持(REFRESH Support)**：DDR3内存需要定期刷新以保持数据的完整性，IP核提供了相应的支持。 8. **本地到内存地址映射(Local-to-Memory Address Mapping)**：解释如何将FPGA内部的地址映射到DDR3内存的地址空间。 9. **模式寄存器编程(Mode Register Programming)**：DDR3内存有多个模式寄存器，用来设置内存的各种工作参数，IP核提供了编程这些寄存器的功能。这份用户指南为开发者提供了详尽的指导，帮助他们在Lattice FPGA平台上有效地集成和使用DDR3 SDRAM Controller IP Core，实现高效、可靠的内存访问。

Functional Description

IPUG80_1.9, October 2016 11 DDR3 SDRAM Controller IP Core User’s Guide

multiple trials. If there is any failure, the memory controller shifts the READ signal position and tries again until it

detects no BURSTDET failure.

The memory controller stores the delay value of the successful position of the READ signal for each DQS group. It

uses these delay values during a normal read operation to correctly detect the preamble first, followed by the gen-

eration of DATAVALID signal.

Selecting READ_PULSE_TAP Value (Only for LatticeECP3 Device)

For every read operation, the DDR3 I/O primitives must be initialized at the appropriate time to identify the incom-

ing DQS preamble in order to generate the data valid signal. For this purpose the controller internally generates a

signal called dqs_read in such a way that this signal’s trailing edge is positioned within the incoming DQS preamble

window.

Due to PCB routing delays, DIMM module routing delays and routing delays within the FPGA, the incoming DQS

signal’s delay varies from board to board. To compensate for this variability in DQS delay, the controller shifts the

internal signal dqs_read in such a way to position it within the preamble time.

Each shift (step) moves the dqs_read signal by one half period of the eclk (1.25ns for 400MHz memory clock).

A port, read_pulse_tap, is provided in the Core top level file ddr3_sdram_mem_top_wrapper.v for the user to load

the shift count for each DQS group. Each DQS group is assigned a 3-bit shift count value in this port, starting with

LSB 3 bits for DQS_0. This count can be any value from 0 to 7.

For the core to work properly on the board, it is recommended that the dqs_read signal be shifted by two steps for

UDIMMs, by four steps for RDIMMs or by one step for on-board memory. Since the Eval simulation environment is

provided without the PCB and FPGA internal routing delays, the recommended values for Eval simulation are: zero

steps for UDIMMs, two steps for RDIMMs or zero steps for on-board memory.

A parameter READ_PULSE_TAP in ddr_p_eval\testbench\tests\ecp3\tb_config_params.v is made available to the

user as an example. This parameter may be loaded to the port read_pulse_tap with appropriate values for simula-

tion and synthesis.

In almost all cases the recommended value is good enough for stable read operations on the board and it is highly

unlikely that the user has to change this value. If there are frequent read errors on the board, the user should try

adjusting the shift count value loaded to the port read_pulse_tap.

Should there be a need to change the READ_PULSE_TAP value, it is suggested that the user starts with changing

the value of DQS7 groups first and then move to adjacent group, if required.

Note: The DDR3 memory controller may fail to generate or improperly generate the read_data_valid signal if the

parameter READ_PULSE_TAP is not loaded to the read_pulse_tap input port or the values are not correct.

Data Path Logic

The Data Path Logic (DPL) block interfaces with the DDR3 I/O modules and is responsible for generating the read

data and read data valid signals during read operations. This block implements all the logic needed to ensure that

the data write/read to and from the memory is transferred to the local user interface in a deterministic and coherent

manner.

Functional Description

IPUG80_1.9, October 2016 12 DDR3 SDRAM Controller IP Core User’s Guide

Signal Descriptions

Table 2-1 describes the user interface and memory interface signals at the top level.

Table 2-1. DDR3 SDRAM Memory Controller Top-Level I/O List

Port Name

Active

State I/O Description

clk_in N/A Input Reference clock to the PLL of the CSM block.

Clock Synchronization Logic (CSM) Interface

sclk N/A Input

System clock used by controller’s core module. User may use

this clock for DDR3 controller interface logic.

eclk N/A Input

Edge clock used by controller’s PHY module. Usually twice the

Frequency of sclk.

sclk2x N/A Input

High speed system clock used by controller’s PHY module.

Usually twice the Frequency of sclk.

wl_rst_datapath High Input

Signal from the PHY to the CSM module triggering a reset to

the DDR primitive. If multiple PHY IPs are implemented in a

design, use an AND gate to feed the wl_rst_datapath signals

from all PHY IPs and connect the output of the AND gate to the

CSM module.

dqsbufd_rst High Output Signal from CSM module to the PHY to reset the DDR primitive.

clocking_good High Input Signal from CSM module indicating stable clock condition.

Local User Interface

rst_n Low Input

Asynchronous reset. By default setting, this signal resets the

entire IP core and the DDR3 memory when asserted. Refer to

“Reset Handling” on page 51 for more details.

mem_rst_n Low Input

Asynchronous reset signal from user to reset the memory

device only. This signal will not reset the memory controller.

Refer to “Reset Handling” on page 51 for more details.

init_start High Input

Initialization start request. Should be asserted to initiate mem-

ory initialization either right after the power-on reset or before

sending the first user command to the memory controller.

Refer to “Initialization Control” on page 14 for more details.

cmd[3:0] N/A Input

User command input to the memory controller. Refer to “User

Commands” on page 16 for available commands.

cmd_valid High Input

Command and address valid input. When asserted, the addr,

cmd, ofly_burst_len and cmd_burst_cnt inputs are considered

valid. Refer to “Command and Address” on page 15 for more

details.

addr[ADDR_WIDTH-1:0] N/A Input

User read or write address input to the memory controller.

Refer the section “Local-to-Memory Address Mapping” for fur-

ther details.

cmd_burst_cnt[4:0] N/A Input

Command burst count input – Indicates the number of times a

given read or write command is to be repeated by the controller

automatically. Controller also generates the address for each

repeated command sequentially as per the burst length of the

command. Burst range is from 1 to 32 and “0” indicates 32 rep-

etitions

ofly_burst_len N/A Input

On-the-fly burst length for current command.

0 = BC4, 1 = BL8.

This input is valid only if Mode Reg0 is set for on-the-fly mode.

If set, this input is sampled when cmd_valid and cmd_rdy are

high.

write_data[DSIZE-1:0] N/A Input

Write data input from user logic to the memory controller. The

user side write data width is four times the memory databus.

Functional Description

IPUG80_1.9, October 2016 13 DDR3 SDRAM Controller IP Core User’s Guide

data_mask[(DSIZE/8)[1:0] High Input

Data mask input for write data. Each bit masks a correspond-

ing byte of local write data.

ext_auto_ref High Input

Refresh request from user – This signal is available only when

the External Auto Refresh Port is selected in the GUI.

init_done High Output

Initialization done output – Asserted for one clock period after

the core completes memory initialization and write leveling.

When sampled high, the input signal init_start must be immedi-

ately deasserted at the same edge of the sampling clock. Refer

to “Initialization Control” on page 14 for more details.

cmd_rdy High Output

Command ready output – When asserted, indicates that the

core is ready to accept the next command and the correspond-

ing address. This cmd_rdy signal is active for one clock period.

datain_rdy High Output

Data ready output – When asserted, indicates the core is

ready to receive the write data.

read_data[DSIZE-1:0] N/A Output Read data output from memory controller to the user logic.

read_data_valid High Output

Read data valid output – When asserted, indicates the data on

the read_data bus is valid.

ext_auto_ref_ack High Output

Completion of memory refresh in response to ext_auto_ref sig-

nal assertion. This pin is available only when the External Auto

Refresh Port is selected in the GUI.

wl_err High Output

Write leveling error. Indicates failure in write leveling. The con-

troller will not work properly if there is a write leveling error.

This signal should be checked when init_done signal is

asserted.

rt_err High Output

Read Training error. Indicates failure in Read Training process.

The controller will not work properly if there is a Read Training

error. This signal should be checked when init_done signal is

asserted. (Only for ECP5 DDR3 IP.)

read_pulse_tap [3*(`DQS_WIDTH)

-1:0]

High Input

Read pulse tap – Count value of 0 to 7 by which the controller's

internal read pulse signal, dqs_read, is to be shifted for proper

read_data_valid signal generation. Default value is 2. Three

bits are allocated for each DQS. (Only for LatticeECP3 DDR3

IP.)

DDR3 SDRAM Memory Interface

em_ddr_reset_n Low Output

Asynchronous reset signal from the controller to the memory

device. Asserted by the controller for the duration of power on

reset or active rst_n or active mem_rst_n. Refer to “Reset Han-

dling” on page 51 for more details.

em_ddr_clk[CLKO_WIDTH-1:0] N/A Output Up to 400 MHz memory clock generated by the controller.

em_ ddr_clk_n[CLKO_WIDTH-1:0] N/A Output

400 MHz complimentary memory clock generated by the con-

troller.

em_ ddr_cke[CKE_WIDTH-1:0] High Output Memory clock enable generated by the controller.

em_ ddr_addr[ROW_WIDTH-1:0] N/A Output

Memory address bus – multiplexed row and column address

for the memory.

em_ ddr_ba[2:0] N/A Output Memory bank address.

em_ ddr_data[DATA_WIDTH-1:0] N/A In/Out Memory bi-directional data bus.

em_ ddr_dm[(DATA_WIDTH/8)-1:0] High Output

DDR3 memory write data mask – to mask the byte lanes for

byte-level write.

em_ ddr_dqs[DQS_WIDTH-1:0] N/A In/Out Memory bi-directional data strobe.

em_ ddr_dqs_n[DQS_WIDTH-1:0] N/A In/Out Memory complimentary bi-directional data strobe

em_ ddr_cs_n[CS_WIDTH-1:0] Low Output Memory chip select.

Table 2-1. DDR3 SDRAM Memory Controller Top-Level I/O List (Continued)

Port Name

Active

State I/O Description

剩余60页未读，继续阅读

DXD_xiaoding

粉丝: 0
资源: 2

Lattice FPGA DDR3控制器用户指南

基于springboot共享经济背景下校园闲置物品交易平台源码数据库文档.zip

基于WoodandBerry1和非耦合控制WoodandBerry2来实现控制木材和浆果蒸馏柱控制Simulink仿真.rar

emcopy042002.zip

(源码)基于Python的遥感图像语义分割系统.zip

(源码)基于Spring Boot的博客管理系统.zip

基于springboot的中医院问诊系统源码数据库文档.zip

基于SpringBoot+Vue的校园篮球联赛管理系统源码数据库文档.zip

基于springboot框架药品购买系统源码数据库文档.zip

人工智能开发项目深度学习项目源码带指导视频一起来动动手

(源码)基于Spring Boot和Vue的基金管理系统.zip

最新资源