"DFI 5.0接口协议详解：DDR5/LPDDR5控制器与PHY对接标准"

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The DDR DFI 5.0 version is a standardized interface protocol specifically designed for the integration of DDR5/LPDDR5 Controller and PHY components. This protocol, known as DFI 5.0, aims to streamline and optimize communication between these two essential components in memory systems. The DDR PHY Interface, Version 5.01, dated April 27, 2018, is a comprehensive specification that outlines the guidelines and protocols for implementing the DFI 5.0 standard. Developed by Cadence Design Systems, Inc., this specification aims to ensure compatibility, reliability, and efficiency in DDR memory systems. The DFI 5.0 Specification covers various aspects of the interface, including signal definitions, timing requirements, command protocols, and data transmission mechanisms. By adhering to this standard, manufacturers can ensure seamless compatibility and interoperability between DDR5/LPDDR5 Controllers and PHYs from different vendors. Overall, the DDR DFI 5.0 version represents a significant milestone in the development of DDR memory technology. By providing a standardized interface protocol, it simplifies the integration process, enhances performance, and promotes interoperability among different components in memory systems. As technology continues to evolve, adherence to standards like DFI 5.0 will be crucial for ensuring the reliability and efficiency of DDR memory systems in the future.

Architecture

16 of 160 DDR PHY Interface, Version 5.0

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2.0 Architecture

The DFI specification requires a DFI clock and DFI-defined signals that must be driven directly by registers referenced to

a rising edge of the DFI clock. There are no rules dictating the source of the DFI clock, nor are there restrictions on how

the DFI-defined signals are received. For DFI interoperability between the MC and the PHY, ensure compatibility in:

• Signal widths

• Interconnect timing

• Timing parameters

• Frequency ratio

• Function

Interconnect timing compatibility between the MC and the PHY at target frequencies is determined by the specification of

the output timing for signals driven and the setup and hold requirements to receive these signals on the DFI per device, as

defined by the device.

The DFI specification does not dictate absolute latencies or a fixed range of values that must be supported by each device.

Certain DFI timing parameters can be specified as fixed values, maximum values, or as constants based on other values in

the system.

DFI timing parameters must be held constant while commands are being executed on the DFI bus; however, if necessary,

DFI timing parameters may be changed during a frequency change or while the bus is in the idle state. For more

information on timing, refer to Section 5.0, “Signal Timing”.

The DFI specification identifies the DFI signals relevant to a specific implementation based upon support for specific

DRAM device(s), optional features and frequency ratio. For more information on which signals are relevant to a specific

implementation, refer to Table 4, “DFI Signal Requirements”.

2.1 Clocking

The DFI bus does not include a clock signal; The DFI clock is generally assumed to be the same clock as the MC clock.

The MC may operate at the same or different clock frequency than the memory. If the DFI clock and the memory clock

are the same frequency, the system is defined as a matched frequency system. If the MC operates at a lower frequency,

either 1:2 or 1:4 ratio to the memory clock, the system is defined as a frequency ratio system. For DRAMs utilizing a

single memory clock, the clock ratio applies to the ratio between the DFI clock and the memory clock. For DRAMs

utilizing a separate command and data clock, the clock ratio applies to the ratio between the DFI clock and the data clock;

the DFI clock and the command clock operate at the same frequency.

DFI defines three clock domains - the control clock domain, the command clock domain, and the data clock domain. For

a matched frequency system, these clock domains operate at the same frequency. For a frequency ratio system with a

single memory clock, the control clock domain operates at the DFI clock frequency, the command and data clock domains

operate at the higher clock ratio; generally referred to as the DFI PHY clock frequency. For a frequency ratio system with

separate command and data clock frequencies, the control clock domain and the command clock domain operate at the

DFI clock frequency and the data clock domain operates at the higher clock ratio. Timing parameters associated with each

clock domain are also defined in reference to the corresponding clock domain.

Architecture

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allow the MC and PHY to transfer all of the DRAM-required data in a single DFI clock cycle. The write data must be

delivered with the DFI data words aligned in ascending order.

For a matched frequency DFI command clock domain system, a single DFI command is issued per DFI clock as required

for a single memory clock of DRAM command; for DDR commands this includes both edges. For a frequency ratio DFI

command clock domain system, a DFI command is issued per phase where the number of command phases is equivalent

to the clock ratio.

• Operating at a matched frequency system, the MC and the PHY operate with a 1:1 ratio.

• Operating at a frequency ratio, the MC and the PHY operate with a common frequency ratio of 1:2 or 1:4.

• The PHY must be able to accept a command on any and all phases.

• The frequency ratio depends on the relationship of the reference clocks for the MC and the PHY. For a PHY

frequency ratio system, the frequency ratio is defined between the DFI clock and the memory clock. For a data

frequency ratio system, the command frequency ratio is matched between the DFI clock and the memory command

clock and the data frequency ratio is between the DFI clock and the memory data clock.

• For signals operating at a frequency ratio, phase-specific signals with a suffix of "_pN", with the phase number N

(e.g., dfi_wrdata_pN), replace the matched frequency signals for the command (if PHY frequency ratio), write

data, read data and WCK control interface signals. Phase-specific signals allow the MC to drive multiple commands

in a single clock cycle.

Data word-specific signals with a suffix of "_wN", with the DFI data word number N (e.g., dfi_rddata_wN),

replace the matched frequency signals for the read interface to distinguish how DRAM words are transferred across

the DFI bus.

Variable pulse width-specific signals with a suffix of "aN", with the PHY clock cycle N (e.g., dfi_alert_n_aN),

replace the matched frequency signals for the status interface to maintain the pulse width during transmission of

error signals from the memory system to the PHY.

For all signal types, the suffix for phase 0/data word 0/clock cycle 0 is optional.

For more information on frequency ratios, refer to Section 4.10, “Frequency Ratios Across the DFI”.

2.2 Optional Protocols

Optional protocols handle data bus inversion (DBI), cyclic redundancy check (CRC), system frequency change,

command/address (CA) parity, low power and the error interface. For more information on optional protocols, refer to

Section 4.6, “Data Bus Inversion”, Section 4.7.3, “Cyclic Redundancy Check”, Section 4.11, “Frequency Change”,

Section 4.12, “CA Parity Signaling and CA Parity, CRC Errors”, Section 4.14, “Error Signaling”, Section , “Figure 78,

“Entering 2N Mode with a Sync Command; DDR4 with Matched Frequency” and Figure 79, “Entering 2N Mode with a

MPC command; DDR5, 1:2 Frequency Ratio” illustrate the difference in entering 2N mode with and without issuing a

sync command.” and Section 4.19, “Use of the WCK Control Interface”.

2.3 DFI Feature Requirements

The DFI specification defines the MC-PHY interface for numerous memory protocols and topologies. Not all DFI

features are applicable or required for any particular memory sub-system. Features are divided into global and memory-

specific features to aid interoperability and optimal system design.

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