IEEE Journal of Solid-State Circuits: Transistor-Level IC Design and Peer Review

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"JSSC-2019-5 是一份由IEEE固态电路学会出版的期刊，专注于固态电路领域，特别是集成电路的晶体管级设计。此期刊的文章经过同行评审，按照IEEE PSPB操作手册的规定进行，采用单盲审稿制度。每篇文章至少由两位独立审稿人进行评审，作者的身份对审稿人保密，但审稿人的身份对作者是公开的。在文章被接受之前，会进行抄袭检查。该期刊是IEEE固态电路学会的成员福利，所有IEEE会员在支付年度学会会费后都可以收到。此外，文章仅供个人使用。" 《IEEE固态电路期刊》（IEEE Journal of Solid-State Circuits）是一个专业平台，发布与固态电路广泛领域的研究成果，特别是关注集成电路上的晶体管级设计。这个领域的研究涵盖了从基础的半导体器件到复杂的系统级集成技术。晶体管级设计是指在电路板或芯片级别上对电子元件的布局、布线和优化，这是集成电路开发的关键步骤。期刊的审稿过程严谨，遵循IEEE的标准，采用单盲评审方式确保公平公正。这意味着审稿人不知道作者的身份，可以更专注于文章的学术质量和研究贡献。审稿人通常是领域内的专家，他们的反馈对于提升论文质量至关重要。此外，抄袭检测确保了发表的内容具有原创性和可信度，维护了学术界的诚信。期刊的出版得益于IEEE固态电路学会的支持，学会为会员提供服务，包括获取这份期刊的权益。学会的领导团队由来自全球各地的知名学者和业界专家组成，他们致力于推动固态电路领域的研究和发展。学会还通过网站（http://sscs.org）为会员提供最新的研究信息和交流平台。 "JSSC-2019-5"代表的不仅是期刊的一期，它体现了固态电路领域的最新进展和专业知识，是研究人员、工程师和学者们交流思想和成果的重要平台。这个平台通过严格的评审流程，保证了发布的每一项工作都是高质量、创新性的，对推动电子科技的发展有着深远的影响。

YANG et al.: 0.2-V ENERGY-HARVESTING BLE TRANSMITTER WITH A MICROPOWER MANAGER 1359

Fig. 23. Measured output spectrum when delivering a single tone at 0 dBm.

Fig. 24. Measured GFSK modulation spectrum.

Fig. 25. Measured (a) eye diagrams for 1-Mbps GFSK modulation;

(b) 425-μs BLE packet in open-loop operation.

active and sleep power at different V

DD,EH

. The total power

consumption at V

DD,EH

= 0.2 V is 3.97 mW, where VCO

and PA draws directly 99% of the dc current. The μPM takes

the remaining 1%. Thus, the μPM improves the TX efﬁciency

mainly at the cost of the chip area. The sleep power of the

whole TX is 5.2 nW, mainly due to the ULV operation and

the use of a negative voltage for power-gating the VCO and

the PA in the sleep mode.

E. Overall TX Powered-Up by a Solar Cell

We also tested the TX under a solar cell (1 × 1cm

) and

conﬁgured it to send a 425-μs signal package under a certain

indoor solar irradiance. The TX draws ∼26 mA at 0.25 V

Fig. 26. Power breakdown of the TX in active (top) and sleep (bottom)

modes at V

DD,EH

= 0.2 and 0.3V.

Fig. 27. Measured output power of TX driven by the solar cell with two

470-μF capacitors, and the open circuit voltage of the solar cell at different

solar irradiance.

given by the reservoir capacitor in parallel the solar cell.

To ensure <10-mV voltage drop on the reservoir capacitor,

the calculated capacitor size should be 1 mF. Considering that

the transient current is larger than the steady-state current,

we placed two 470-μF capacitors in parallel with the solar

cell. If we also add a 0.2-F supercapacitor in parallel with the

solar cell, the TX can still operate >0.5 h when the light is

OFF. Fig. 27 shows the transient output voltage of the solar

cell and P

out

of the TX at different solar irradiance. The TX

works properly at the solar irradiance down to 50 μW/cm

which fully covers the indoor artiﬁcial lighting range [23].

Fig. 28 exhibits the transient output voltage of the solar cell

loaded by the TX with a 600-μs width of enable pulse signal

per second, under an indoor irradiance of 70 μW/cm

.The

output voltage of the solar cell drops from 245 to 237 mV

during the enable pulse signal, and will be recharged to

245 mV within 550 ms. This charging time can be further

reduced by introducing a maximum power point tracking

circuit. Fig. 29 displays the startup time of the TX that is

<200 μs. The P

out

variation is <1dBandthe f

OUT

drift

is <40 kHz for a data transmission duration of 425 μs

which complies with the BLE standard [24]. Note that the

dynamic f

OUT

drift is not the same as the static f

OUT

pushing,

the simulated f

OUT

drift is <30 kHz close to the measured

result.

YANG et al.: 0.2-V ENERGY-HARVESTING BLE TRANSMITTER WITH A MICROPOWER MANAGER 1361

entails another supply (0.7 or 1 V), which implies the need

of a power-management unit in the system level to interface

with the sub-0.5V energy-harvesting sources. Here, our type-I

analog PLL using a dynamic MSSF favors ULV operation and

reveals itself as very power efﬁcient (0.29 mW/GHz excluding

the VCO). Our ULV VCO and PA are also competitive in

terms of RF performances. No external matching network is

necessary for the PA, and we were able to manage the sleep

power down to 5.2 nW via proper power-gating.

VI. C

ONCLUSION

This paper reported the design of a BLE TX aided by a

fully integrated μPM to allow direct powering by a single

0.2-V supply. The four key techniques are: 1) a μPM that

generates and stabilizes all internal biases and supplies against

DD,EH

variation, and provides an always-on negative voltage

as the gate bias of the VCO and PA suppress their leakage

power in the sleep mode; 2) an ULV VCO with gate-to-source

transformer coupling to enhance the output swing and improve

the PN; 3) an ULV Class-E/F

PA with an inside-transformer

LC notch to suppress the HD

; and 4) a type-I integer-N

analog PLL with an MSSF of 5% duty cycle to suppress the

jitter and reference spurs. Fabricated in 28-nm CMOS, the TX

achieves 25% system efﬁciency at 0-dBm P

out

, and the sleep

power is 5.2 nW. The open-loop GFSK modulation shows an

FSK error of 2.84%, and the output harmonics comply with the

BLE speciﬁcation without resorting from any explicit ﬁlters or

external components.

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Shiheng Yang (S’15) received the B.Sc. degree in

electrical and electronics engineering from the Uni-

versity of Macau, Macau, China, in 2014, where he

is currently pursuing the Ph.D. degree in electronic

and computer engineering.

He received the SJM and Frank Wong Foundation

Scholarships for outstanding academic achievement.

He was the Founding Chairman of the Faculty

of Science and Technology Postgraduate Students,

University of Macau. His research interests include

analog/mixed IC designs and RF circuits, specializ-

inginthePLL.

Dr. Yang currently serves as a Reviewer for the IEEE J

OURNAL OF

SOLID-STATE CIRCUITS and the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS I and II.

1362 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 5, MAY 2019

Jun Yin (M’14) received the B.Sc. and M.Sc.

degrees in microelectronics from Peking University,

Beijing, China, in 2004 and 2007, respectively, and

the Ph.D. degree in electronic and computer engi-

neering from the Hong Kong University of Science

and Technology, Hong Kong, in 2013.

He is currently an Assistant Professor with the

State Key Laboratory of Analog and Mixed-Signal

VLSI, University of Macau, Macau, China. His

research interests are on the CMOS RF inte-

grated circuits for wireless communication and radar

systems.

Haidong Yi (S’16) received the B.Sc. degree in

electronic science and technology from Henan Uni-

versity, Kaifeng, China, in 2012, and the M.Eng.

degree in microelectronics from Fudan University,

Shanghai, China, in 2015. He is currently pursu-

ing the Ph.D. degree in electronic and computer

engineering with the University of Macau, Macau,

China, with a focus on ultralow-voltage low-power

analog and RF circuit techniques.

Wei-Han Yu (S’09) received the B.Sc. and M.Sc.

degrees in electrical and electronics engineering

from the University of Macau (UM), Macau, China,

in 2010 and 2012, respectively, and the Ph.D.

degree from the Faculty of Science and Technology,

State-Key Laboratory of Analog and Mixed-Signal

VLSI, Department of Electronic and Computer Engi-

neering, UM, in 2018.

His current research interests include RF and

mmwave transmitter, power ampliﬁer, digital pre-

distortion, and EM modeling for next-generation

mobile communications.

Dr. Yu is currently a Macau Fellow with microelectronics at UM. He was

a recipient the IEEE ISSCC STGA Award and the FDCT S&T Postgraduate

Student Award in 2016 and the IEEE SSCS Predoctoral Achievement Award

in 2018.

Pui-In Mak (S’00–M’08–SM’11–F’19) received the

Ph.D. degree from the University of Macau (UM),

Macau, China, in 2006.

He is currently a Full Professor with the Faculty

of Science and Technology, Department of Electrical

and Computer Engineering, UM, where he is also

an Associate Director (Research) with the State Key

Laboratory of Analog and Mixed-Signal VLSI. His

research interests include analog and radio frequency

circuits and systems for wireless and multidiscipli-

nary innovations.

Prof. Mak is a Fellow of the IET. He was a TPC Vice Co-Chair of ASP-DAC

in 2016, TPC Member of A-SSCC from 2013 to 2016, ESSCIRC from

2016 to 2017, and ISSCC from 2017 to 2019. He was a member of the

Board-of-Governors of the IEEE C

IRCUITS AND SYSTEMS SOCIETY from

2009 to 2011. He has been a Distinguished Lecturer of the IEEE Circuits

and Systems Society from 2014 to 2015 and the IEEE Solid-State Circuits

Society from 2017 to 2018. He was a co-recipient of the DAC/ISSCC Student

Paper Award in 2005, the CASS Outstanding Young Author Award in 2010,

the National Scientiﬁc and Technological Progress Award in 2011, the Best

Associate Editor of IEEE T

RANSACTIONS ON CIRCUITS AND SYSTEMS II

from 2012 to 2013, the A-SSCC Distinguished Design Award in 2015,

the ISSCC Silkroad Award in 2016, and the Honorary Title of Value for

Scientiﬁc Merits by the Macau Government in 2005. He was the Editorial

Board Member of IEEE Press from 2014 to 2016, the Senior Editor of

IEEE J

OURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND

SYSTEMS from 2014 to 2015, an Associate Editor of the IEEE JOURNAL

SOLID-STATE CIRCUITS since 2018, the IEEE SOLID-STATE CIRCUITS

LETTERS since 2017, and the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS I from 2010 to 2011, from 2014 to 2015, and the IEEE TRANSAC-

TIONS ON CIRCUITS AND SYSTEMS II from 2010 to 2013. He is currently a

Distinguished Lecturer of the IEEE Circuits and Systems Society since 2018.

He has been inducted as an Overseas Expert of the Chinese Academy of

Sciences since 2018.

Rui P. Martins (M’88–SM’99–F’08), was born

in 1957. He received the bachelor’s degree, master’s,

Ph.D., and the Habilitation degrees for Full Professor

in electrical engineering and computers from the

Department of Electrical and Computer Engineering,

Instituto Superior Técnico (IST), Universidade de

Lisboa, Lisbon, Portugal, in 1980, 1985, 1992, and

2001, respectively.

Since 1980, he has been with the Department of

Electrical and Computer Engineering (DECE), IST.

Since 1992, he has been on leave from IST. He is

currently with the Faculty of Science and Technology (FST), Department of

Electrical and Computer Engineering, University of Macau (UM), Macau,

China, where he has been a Chair Professor since 2013. From 1994 to 1997,

he was the Dean of the Faculty of the FST. Since 1997, he has been a

Vice-Rector with the University of Macau. From 2008 to 2018, he was a

Vice-Rector (Research) and a Vice-Rector Global Affairs since 2018. He was

a co-founder of Synopsys, Macau, from 2001 to 2002, and created in 2003,

the Analog and Mixed-Signal VLSI Research Laboratory, UM, elevated in

2011 to State Key Laboratory of China (the ﬁrst in Engineering in Macau),

where he became a Founding Director. Within the scope of his teaching and

research activities, he has taught 21 bachelor and master courses and at UM,

has supervised (or co-supervised) 45 theses, Ph.D. (24) and master’s (21).

He has co-authored seven books and 11 book chapters, 466 papers, in scientiﬁc

journals (162) and in conference proceedings (304), and 64 academic works,

in a total of 580 publications. He holds 30 U.S. patents and two Taiwan

patents.

Dr. Martins was a Nominations Committee Member of the IEEE CASS

in 2016 and a member of the IEEE CASS Fellow Evaluation Committee

in 2013, 2014, and 2019. He was a Founding Chairman of both the IEEE

Macau Section from 2003 to 2005 and the IEEE Macau Joint-Chapter on

CAS/COM from 2005 to 2008 [2009 World Chapter of the Year of IEEE

CAS Society]. He was the General Chair of the 2008 IEEE Asia–Paciﬁc

Conference on CAS—APCCAS’2008 and was a Vice President of Region

10 (Asia, Australia, and the Paciﬁc) of the IEEE CASS from 2009 to

2011. He was a Vice-President (World) of the Regional Activities and

Membership of the IEEE CASS from 2012 to 2013. He was the CAS

Society representative in the Nominating Committee, for the election in 2014,

of the Division I (CASS/EDS/SSCS)—Director of the IEEE. He was the

General Chair of the ACM/IEEE Asia South Paciﬁc Design Automation

Conference—ASP-DAC’2016. He was the Chair of the IEEE CASS Fellow

Evaluation Committee in 2018.. In 2010 was elected, unanimously, as a

Corresponding Member of the Portuguese Academy of Sciences in Lisbon,

is the only Portuguese Academician living in Asia. He was a recipient of

two government decorations: the Medal of Professional Merit from Macau

Government (Portuguese Administration) in 1999, the Honorary Title of Value

from Macau SAR Government (Chinese Administration) in 2001, the IEEE

Council on Electronic Design Automation Outstanding Service Award 2016,

and nominated Best Associate Editor of T

RANSACTIONS ON CAS II from

2012 to 2013. He served as an Associate Editor for the IEEE TCAS II:

XPRESS BRIEFS from 2010 to 2013.

1446 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 5, MAY 2019

A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR

ADC With an Open-Loop MDAC

Chao Wu and Jie Yuan , Senior Member, IEEE

Abstract—Compared to pipelined analog-to-digital convert-

ers (ADCs), pipelined- successive approximation register (SAR)

ADCs have been actively explored for better energy efﬁciency

in recent years. Nonetheless, the pipelined-SAR architecture

inherently limits the sampling speed of the ADC due to the slow

operation of the ﬁrst SAR ADC, which becomes an increasingly

important limitation with the recent expansion of high-speed

applications. In this paper, we introduce our new design of a

pipelined-SAR ADC to enable faster speed. New loop-unrolled

architecture with the split capacitor is used for the ﬁrst SAR ADC

to improve the speed. A resistive open-loop multiplying digital-

to-analog converter with a new calibration scheme is designed

to reduce the power consumption at high speed. As a result, the

65-nm design can achieve 300-MS/s sampling rate with a single

channel. It is among the fastest pipelined-SAR ADC design so far.

The peak signal-to-noise-and-distortion ratio is 63.6 dB with a

10-MHz input. It consumes 12.5-mW power from a 1.2-V supply

to achieve a power efﬁciency of 34 fJ/conversion-step.

Index Terms— Calibration technique, high-speed analog-to-

digital converter (ADC), loop-unrolled successive approxima-

tion register (SAR), open-loop multiplying digital-to-analog

converter (MDAC), pipelined-SAR ADC.

I. INTRODUCTION

IGH-SPEED high-precision analog-to-digital converters

(ADCs) are widely used in various ﬁelds, such as image

processing, information storage, and wireless communica-

tion [1]–[3]. Pipelined ADC is the primary candidate for these

applications. Time interleaving [4] is actively researched to

achieve speed higher than single-channel ADCs. Power con-

sumption is a major limiting factor in these systems. Various

techniques, such as OPAMP sharing [5]–[7] and multi-bit

multiplying digital-to-analog converter (MDAC) [8], have

been actively explored to reduce the pipelined ADC power

by reducing the number of OPAMPs in the pipeline. More

recently, pipelined-successive approximation register (SAR)

ADCs have been actively researched to combine low-powered

SAR ADC into the pipeline [9]–[11]. By using SAR ADCs

as the sub-ADCs in the pipeline, a high-resolution pipelined

ADC can be designed with only two stages. Hence, only one

OPAMP is needed for a whole pipelined-SAR ADC, which

could further reduce the pipelined ADC power.

Manuscript received June 12, 2018; revised August 19, 2018 and

October 11, 2018; accepted December 3, 2018. Date of publication January 4,

2019; date of current version April 23, 2019. This paper was approved

by Associate Editor Piero Malcovati. This work was supported by the

RGC General Research Fund sponsored by the Research Grants Council of

Hong Kong under Project GRF 16212014. (Corresponding author: Jie Yuan.)

The authors are with the Department of Electronic and Computer Engi-

neering, The Hong Kong University of Science and Technology, Hong Kong

(e-mail: eeyuan@ust.hk).

Color versions of one or more of the ﬁgures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/JSSC.2018.2886327

With a better power efﬁciency, pipelined-SAR ADCs have

been explored for high-speed applications. However, the speed

of pipelined-SAR ADCs is limited. The critical issue is that the

quantization time of a 6-bit SAR ADC is much longer than

the conventional ﬂash sub-ADCs. This additional delay will

erode the time available for either sampling or ampliﬁcation.

In [9], the sampling time was shrunk to accommodate this

additional SAR ADC bit-cycling time. Improvement has also

been made on the speed of the SAR ADC. In [12], a loop-

unrolled asynchronous SAR ADC was used to eliminate

the SAR logic delay from the critical path. The bit-cycling

period was shortened. In this loop-unrolled architecture, N

comparators were used to resolve N-bit resolution. The indi-

vidual comparator offset requires calibration. As mentioned

in [13], the input common-mode voltage of comparators would

drop during bit cycles which results in offset drifts. Hence,

the foreground offset calibration in [12] cannot address the

offset issue effectively.

The power consumption of a pipelined-SAR ADC is domi-

nated by the OPAMP in the conventional closed-loop MDAC.

It has been shown in [8] that a high-resolution ﬁrst stage

leads to the demand of large OPAMP gain-bandwidth (GBW)

product and high OPAMP dc gain. In recent sub-micrometer

CMOS processes, it needs large power consumption to push

up the non-dominant poles while maintaining reasonably high

gain in an OPAMP. In [14] and [15], open-loop MDAC was

used to save the power. However, the process variation and

non-linearity are the major bottlenecks for open-loop MDACs.

Complicated non-linear gain calibration was needed [15],

which limits the application of open-loop MDACs. In [12]

and [16]–[18], constant-slewing dynamic ampliﬁers were used

in an open-loop MDAC. This architecture further reduces

power, but the MDAC gain is not only sensitive to the

process variation but also to any change in the transient

settling process, such as clock jitter and supply spikes. In [19],

a passive residue transfer technique was introduced to remove

the MDAC completely. Hence, there is no gain for the residual

voltage, which demands very stringent noise and offset control

on the backend.

In this paper, our focus is on the speed of pipelined-SAR

ADCs. We analyzed the speed limitation of the pipelined-

SAR architecture, and found that, for sampling speed beyond

200 MS/s, the SAR ADC generally limits the ADC sampling

speed in the 65-nm CMOS processes. In order to design a

pipelined-SAR ADC with higher speed, we developed a new

asynchronous loop-unrolled SAR ADC with split capacitor to

maximize the speed of the SAR ADC. To reduce the gain

sensitivity to static process voltage temperature (PVT) spread

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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