RDA Microelectronics, Inc. RDA5820 FM Transceiver V1.3
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA. Page 5 of 28
3.8 Synthesizer2
The frequency synthesizer 2 (including
synthesizer2 and VCO2 ) generates clock
signals for ADC under FM RX (receive) mode.
The frequency synthesizer2 is also the FM
transmit core. The digital signals (audio) are
directly added on it.
3.9 Power Supply
The RDA5820 integrated one LDO which supplies
power to the chip. The external supply voltage
range is 2.7-5.5 V.
3.10 RESET and Control Interface select
The RDA5820 is RESET itself When VIO is Power
up. And also support soft reset by trigger 02H
BIT1 from 0 to 1. The control interface is selected
by MODE Pin. The MODE Pin is low ,I2C
Interface is selected. The MODE Pin is set to VIO,
SPI Interface is selected.
3.11 Control Interface
The RDA5820 supports three-wire and I
2
C control
interface. User could select either of them to
program the chip.
The three-wire interface is a standard SPI
interface. It includes three pins: SEN, SCLK and
SDIO. Each register write is 25-bit long, including
4-bit high register address, a r/w bit, 4-bit low
register address, and 16-bit data (MSB is the first
bit). RDA5820 samples command byte and data
at posedge of SCLK. Each register read is also
25-bit long, including 4-bit high register address, a
r/w bit, 4-bit low register address, and 16-bit data
(MSB is the first bit) from RDA5820. The turn
around cycle between command byte from MCU
and data from RDA5820 is a half cycle. RDA5820
samples command byte at posedge of SCLK, and
output data also at posedge of SCLK.
The I
2
C interface is compliant to I
2
C Bus
Specification 2.1. It includes two pins: SCLK and
SDIO. A I
2
C interface transfer begins with START
condition, a command byte and data bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (0010001b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes
is read out from RDA5820.
Details refer to RDA5820 Programming Guide.
3.12 I
2
S Audio Data Interface
The RDA5820 supports I
2
S (Inter_IC Sound Bus)
audio interface. The interface is fully compliant
with I
2
S bus specification. When setting I2SEN bit
high, RDA5820 will output SCK, WS, SD signals
from GPIO3, GPIO1, GPIO2 as I
2
S master and
transmitter, the sample rate is 48Kbps ，
44.1kbps,32kbps….. RDA5820 also support as
I
2
S slaver mode and transmitter, the sample rate
is less than 100kbps.
3.13 GPIO Outputs
The RDA5820 has three GPIOs. The function of
GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is set to low, GPIO pins could be
programmed to output low or high or high-Z, or be
programmed to output interrupt and stereo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 could be programmed to
output a low interrupt (interrupt will be generated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VA and VD
supplies or the ENABLE bit.
Figure 3-2. I2S Digital Audio Format
SCK
MSB
SD
WS
1 SCK
LEFT CHANNEL
LSB MSB
1 SCK
RIGHT CHANNEL
LSB
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