探索DSP外围电路设计经典：接口与系统管理

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本资源是一本经典的DSP外部电路设计指南，深入探讨了数字信号处理器（DSP）与外界硬件世界的接口问题。在第四章中，作者首先从DSP设备的核心功能扩展出发，解释了如何实现高效的数据传输和处理，这依赖于DSP设备快速处理大量数据的能力，以及内置的外围管理模块。 "4.1 DSP设备——超越核心"部分，作者将焦点转向了DSP系统的外围特性，讨论了这些组件如何超越简单的计算核心，提供更全面的功能。这可能包括高级定时器、中断控制器、内存管理和接口模块等，这些都对整体系统性能有重大影响。 "4.2 硬件接口和I/O控制"是关键章节，讲解了如何设计和实现DSP与外设之间的物理连接，如串行/并行端口、总线接口、GPIO（通用输入/输出）等，以确保数据流的顺畅和指令的有效传递。同时，还涉及到了I/O控制策略，如同步与异步通信、中断管理等。 "4.3 系统管理和控制"这部分着重于处理器的系统级管理，如何通过软件或硬件机制来监控、配置和调整DSP的工作状态，例如设置时钟频率、电源管理、任务调度等，以适应不同的应用场景和优化性能。 "4.4 全部的模拟部件（如ADC、DAC、抗混叠滤波、过采样等）"这部分详细论述了与数字世界交互的模拟信号处理部分。在现代DSP设计中，除了数字信号处理，模拟信号的转换和处理也是必不可少的，因此这部分内容会涉及如何正确集成和利用模拟电路，以实现信号的完整流程，如信号的数字化输入（ADC）、数字到模拟转换（DAC），以及防止信号失真的预处理技术。这本书为读者提供了丰富的实践指导，不仅涵盖了理论知识，还结合实际案例，特别是来自TI公司的产品，帮助设计师理解和应用DSP的外围电路设计技巧，从而构建出高效、稳定和可扩展的数字信号处理系统。

C6xxx EVM, the evaluation board provided by Texas Instruments. The addition to the on-

chip memory mentioned in the previous section, the EVM provides two external memory

areas, one of which is very fast and the other not so fast. The first area of external memory

is a 64K×32-bit memory bank which runs at the full 133 MHz bus speed, i.e. with an

access time of 7.5 ns. The second external memory area is in the form of two banks of

1M×32-bit SBRAM with an access time of 10 ns, i.e. the external bus can only run at 100

MHz when accessing this memory. An expansion memory connector is also provided to

enable asynchronous memory and memory-mapped devices to be added using a daugh-

terboard. The memory arrangement is shown in Figure 4.9.

The External Memory Interface, EMIF, address and data busses are buffered as soon as

they exit the DSP chip in order to preserve signal integrity. Buffering is important when

using external busses because timing errors and loading effects can easily give problems

when running at high speeds. A 32-bit bus switch is also used to isolate the rest of the data

bus during SBSRAM accesses, as shown in Figure 4.9. This isolation preserves signal

integrity and allows the EVM to run the SBSRAM at the full 133 MHz bus speed.

Very fast line drivers are used to buffer the address and control signals, which limits the

loading on the DSPs outputs. Also, fast data transceivers are used to provide voltage trans-

lation and the necessary drive to the expansion connector on the EVM board. The

complete memory map for the C6xxx EVM board is shown in Table 4.4. The memory

map shown is that of configuration MAP-0 and hence the external SBRAM is mapped

into the memory space starting at address zero.

Although it is quite reasonable to expect a DSP device to be able to access on-chip periph-

erals at the full internal bus speed, it is quite likely that not all external devices will operate

at this full speed. This is particularly true of external read only memories, ROMs, which

DSP devices – beyond the core 219

32-bit bus switch

Buffer

TI C6x

DSP

SBSRAM

133 MHz

64k×32

Expansion memory

connector and buffer

SDRAM

100 MHz

1M×32

SDRAM

100 MHz

1M×32

32-bit data bus

Figure 4.9 TI C6xxx

EVM external memory

configuration

Wait state generator – coping with slow memory 4.1.4

are generally only used at start up during the boot procedure. Clearly slower memories are

cheaper so it is often a matter of providing a DSP system with the minimal amount of fast

memory and using slower memory devices wherever possible. External memory-mapped

I/O devices, such as AD/DA converters and CODECs may also not be able to interface to

the DSP at the full operating speed. For this reason most DSP devices incorporate a mech-

anism by which the external busses may be slowed down momentarily during an access to

a slow device. The mechanism uses a technique where extra clock cycles are inserted

during the external bus access: these extra clock cycles are referred to as wait states. Wait

state insertion can be implemented in hardware by the addition of a small amount of

220 Chapter 4 ❚ DSP systems – interfacing with the outside world

Table 4.4 Texas

Instruments C6xxx

EVM board, MAP-0

memory map

External

Memory Size

Start Address End Address Space (Bytes) Description

00000000 0003FFFF CE0 256K SBSRAM

00040000 00FFFFFF CE0 16M – 256K Unused

01000000 012FFFFF CE1 3M Asynchronous expansion memory

01300000 0130003F CE1 64 PCI add-on registers

01300040 0130FFFF CE1 64K – 64 Unavailable

01310000 01310003 CE1 4 PCI FIFO

01310004 0131FFFF CE1 16 Audio codec registers

01320000 0132FFFF CE1 64K – 16 Unavailable

01320010 0137FFFF CE1 320K Reserved

01380000 0138001F CE1 32 DSP control/status registers

01380020 0138FFFF CE1 64K – 32 Unavailable

01380000 0x13FFFF CE1 448K Reserved

01400000 0140FFFF N/A 64K Internal program memory (IPM)

01410000 017FFFFF N/A 4M – 64K Reserved (future IPM)

01800000 01BFFFFF N/A 4M Internal peripherals

01C00000 01FFFFFF N/A 4M Reserved

02000000 023FFFFF CE2 4M SDRAM (bank 0) or optional

asynchronous expansion memory

02400000 02FFFFFF CE2 12M Reserved

03000000 033FFFFF CE3 4M SDRAM (bank 1) or optional

asynchronous expansion memory

03400000 03FFFFFF CE3 12M Reserved

04000000 7FFFFFFF N/A 1984M Reserved

80000000 8000FFFF N/A 64K Internal data memory (IDM)

80010000 803FFFFF N/A 4M – 64K Reserved (future IDM)

80400000 FFFFFFFF N/A 2044M Reserved

external logic which holds a control pin on the DSP in an inactive state until the external

device is ready to respond. More typically on current DSP devices, wait state insertion is

implemented under software control and the necessary wait state logic is incorporated

into the DSPs own internal circuitry.

On the Texas Instruments C54x DSP, a software programmable wait state generator is

provided which can extend external bus cycles up to seven machine cycles so that very

slow external devices can be interfaced. The software wait state generator is incorporated

without any external hardware. For off-chip memory accesses, from zero to seven wait

states can be specified within the software wait state register, SWWSR. For software wait

state purposes the external address space is divided up into different regions, each of

which can be independently controlled by the SWWSR. The division of external program

and data I/O space is summarized in Table 4.5. Figure 4.10 shows the bus timing of the

C54x DSP when a read–read–write access is made to external memory with no wait states

inserted. In comparison Figure 4.11 shows the same access but this time to slower

memory with a single wait state inserted.

Although the C54x DSP provides software control over external wait state insertion,

external devices requiring more than seven wait states can be interfaced using the hard-

ware READY line. When all external accesses are configured for zero wait states, the

software wait state generator is shut down and placed into a low power state.

As already mentioned, the software programmable wait state generator used on the

C54x DSP is controlled by the 16-bit software wait state register, SWWSR. The SWWSR

is used to control the two program and data spaces, each consisting of two 32 kword

blocks and the I/O space consisting of one 64 kword block. Each of these blocks has a

corresponding 3-bit field in the SWWSR. These fields are shown in Figure 4.12 and

described in Table 4.5.

The value stored in each of the 3-bit fields of the SWWSR identifies the number of

wait states to be inserted when accessing each of the memory areas, as defined in Table

4.5. Between 0 and 7 wait states can be inserted, corresponding to the 3-bit binary

number stored in the SWWSR register fields. The minimum value, which adds no wait

DSP devices – beyond the core 221

Figure 4.10 Memory

access at full speed,

i.e. with no wait state

insertion

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