TMS320VC5416 DSP芯片数据手册

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"TMS320VC5416是一款固定点数字信号处理器的数据手册，由Texas Instruments出版，编号SPRS095O，最初发布于1999年3月，最后修订于2005年1月。文档包含了生产数据信息，但并不保证涵盖所有参数的测试。此外，该资料提供了关于TMS320VC5416的修订历史，主要集中在技术更新和内容修正上。" TMS320VC5416是Texas Instruments公司推出的一款高性能固定点数字信号处理器（DSP），它专门设计用于处理数字信号处理任务，如音频处理、图像处理、通信等领域。这款芯片的核心特点是其高效的计算能力，适合在需要大量快速数学运算的应用中使用。在技术规格方面，TMS320VC5416的数据手册中提到了I/O电流限制的变化。在第五章的第2节中，输出高电流（IOH）从-2mA更改为-8mA，输出低电流（IOL）从2mA更改为8mA。这表明该处理器的输出驱动能力有所增强，能够提供更大的电流来驱动外部电路。同时，第2注释也进行了更新，指出这些输出电流限制适用于VOL（输出低电平）和VOH（输出高电平）的测试条件，除非另有说明。第六章中，原有的第6.2节被删除，可能是为了防止与产品信息的重复。这可能意味着这部分内容已被整合到其他章节或者是在其他文档中详细阐述。在使用TMS320VC5416时，设计者需要参考此数据手册来了解芯片的电气特性、引脚配置、操作条件、功耗信息以及编程接口等关键信息。该处理器的性能和功能会直接影响到整个系统的设计和性能优化。因此，理解并正确应用这些技术参数对于成功地开发基于TMS320VC5416的系统至关重要。 TMS320VC5416是一款强大的数字信号处理器，其固定点架构提供了高精度和高速度的运算能力，适用于各种需要实时信号处理的场合。通过不断的技术更新和修正，确保了该芯片能适应不断变化的市场需求和技术挑战。设计者在使用这款芯片时，必须密切关注其最新的数据手册，以获取最准确的技术信息和指导。

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3 Functional Overview

GPIO

MBus

64K RAM

Dual Access

Program/Data

McBSP1

McBSP2

McBSP3

RHEA Bus

APLL

TIMER

JTAG

Clocks

RHEAbus

RHEA

Bridge

TI BUS

xDMA

logic

16K Program

ROM

Pbus

Cbus

Dbus

Ebus

RHEA bus

MBus

Pbus

Ebus

Pbus

Cbus

Dbus

Ebus

Pbus

Enhanced XIO

P, C, D, E Buses and Control Signals

XIO

16HPI

54X cLEAD

16 HPI

64K RAM

Single Access

Program

3.1 Memory

3.1.1 Data Memory

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 2-2. Signal Descriptions (continued)

TERMINAL

I/O

(1)

DESCRIPTION

NAME

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/ OFF is used as an interrupt to or from the

emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is

driven low, EMU1/ OFF is configured as OFF. The EMU1/ OFF signal, when active low, puts all output drivers into

the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for

EMU1/ OFF

(6)

I/O/Z

multiprocessing applications). Therefore, for the OFF condition, the following apply:

TRST = low,

EMU0 = high

EMU1/ OFF = low

The following functional overview is based on the block diagram in Figure 3-1 .

Figure 3-1. TMS320VC5416 Functional Block Diagram

The device provides both on-chip ROM and RAM memories to aid in system performance and integration.

The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the

on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds,

the device automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

• Higher performance because no wait states are required

• Higher performance because of better flow within the pipeline of the central arithmetic logic unit

(CALU)

• Lower cost than external memory

16 Functional Overview

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3.1.2 Program Memory

3.1.3 Extended Program Memory

3.2 On-Chip ROM With Bootloader

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Software can configure their memory cells to reside inside or outside of the program address map. When

the cells are mapped into program space, the device automatically accesses them when their addresses

are within bounds. When the program-address generation (PAGEN) logic generates an address outside its

bounds, the device automatically generates an external access. The advantages of operating from on-chip

memory are as follows:

• Higher performance because no wait states are required

• Lower cost than external memory

• Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

The device uses a paged extended memory scheme in program space to allow access of up to 8192K of

program memory. In order to implement this scheme, the device includes several features which are also

present on C548/549/5410:

• Twenty-three address lines, instead of sixteen

• An extra memory-mapped register, the XPC

• Six extra instructions for addressing extended program space

Program memory in the device is organized into 128 pages that are each 64K in length.

The value of the XPC register defines the page selection. This register is memory-mapped into data space

to address 001Eh. At a hardware reset, the XPC is initialized to 0.

The device features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program

memory space.

Customers can arrange to have the ROM of the device programmed with contents unique to any particular

application.

A bootloader is available in the standard on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If MP/ MC of

the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip

ROM. This location contains a branch instruction to the start of the bootloader program.

The standard devices provide different ways to download the code to accommodate various system

requirements:

• Parallel from 8-bit or 16-bit-wide EPROM

• Parallel from I/O space, 8-bit or 16-bit mode

• Serial boot from serial ports, 8-bit or 16-bit mode

• Host-port interface boot

• Warm boot

18 Functional Overview

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3.3 On-Chip RAM

3.4 On-Chip Memory Security

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

The standard on-chip ROM layout is shown in Table 3-1 .

Table 3-1. Standard On-Chip ROM Layout

ADDRESS RANGE DESCRIPTION

C000h-D4FFh ROM tables for the GSM EFR speech codec

D500h-F7FFh Reserved

F800h-FBFFh Bootloader

FC00h-FCFFh µ-Law expansion table

FD00h-FDFFh A-Law expansion table

FE00h-FEFFh Sine look-up table

FF00h-FF7Fh Reserved

(1)

FF80h-FFFFh Interrupt vector table

(1) In the ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must

reserve these 128 words at addresses FF00h-FF7Fh in program space.

The device contains 64K-word × 16-bit of on-chip dual-access RAM (DARAM) and 64K-word × 16-bit of

on-chip single-access RAM (SARAM).

The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two

reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address

range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit

to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program

space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into

data space by setting the DROM bit to one.

The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access

memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a

data word is written to another SARAM block. The SARAM is located in the address range

28000h-2FFFFh, and 38000h-3FFFFh in program space.

The device has a maskable option to protect the contents of on-chip memories.

When the RAM/ROM security option is selected, the following restrictions apply:

• Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM

and external RAM originating instruction can not read data from ROM: instead 0FFFFh is read. Code

can still branch to ROM from on-chip RAM or external program memory.

• The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external

memory. To protect the internal RAM, the user must never branch to external memory.

• The security feature completely disables the scan-based emulation capability of the 54x to prevent the

use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG

boundary scan test capability.

• The device is internally forced into microcomputer mode at reset (MP/ MC bit forced to zero),

preventing the ROM from being disabled by the external MP/ MC pin. The status of the MP/ MC bit in

the PMST register can be changed after reset by the user application.

• HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range.

Functional Overview 19

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3.5 Memory Map

Reserved

(OVLY = 1)

External

(OVLY = 0)

Page 0 Program

Hex

Data

On-Chip

DARAM0−3

(OVLY = 1)

External

(OVLY = 0)

MP/MC= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F

0080

FFFF

Interrupts

(External)

FF80

Memory-Mapped

Registers

On-Chip

DARAM0−3

(32K x 16-bit)

On-Chip

DARAM4−7

(DROM=1)

External

(DROM=0)

0080

FFFF

FF7F

0060

007F

0000

Hex

External

Scratch-Pad

RAM

005F

On-Chip ROM

(4K x 16-bit)

Interrupts

(On-Chip)

7FFF

8000

Page 0 Program

Hex

0000

007F

0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

FF80

FF7F

External

7FFF

8000

Reserved

FF00

FEFF

C000

BFFF

8000

7FFF

On-Chip

DARAM0−3

(OVLY = 1)

External

(OVLY = 0)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

If the ROM-only security option is selected the following restrictions apply:

• Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM

and external RAM originating instruction cannot read data from ROM: instead 0FFFFh is read. Code

can still branch to ROM from on-chip RAM or external program memory.

• The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external

memory. To protect the internal RAM the user must never branch to external memory.

• The security feature completely disables the scan-based emulation capability of the 54x to prevent the

use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG

boundary scan test capability.

• The device can be started in either microcomputer mode or microprocessor mode at reset (depends on

the MP/ MC pin).

• HPI read and writes have no restriction.

The program and data memory map is shown in Figure 3-2 . Address ranges for on-chip DARAM in data

memory are:

• DARAM0: 0080h-1FFFh

• DARAM1: 2000h-3FFFh

• DARAM2: 4000h-5FFFh

• DARAM3: 6000h-7FFFh

• DARAM4: 8000h-9FFFh

• DARAM5: A000h-BFFFh

• DARAM6: C000h-DFFFh

• DARAM7: E000h-FFFFh

Figure 3-2. Program and Data Memory Map

20 Functional Overview

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