BlueNRG-LP: Bluetooth 5.2 SoC 数据手册

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"ST公司的Bluenrg-lp是一款支持蓝牙5.2规范的低功耗系统级芯片（SoC），提供了2Mbps的数据速率、长距离（Coded PHY）、广告扩展、通道选择算法#2和GATT缓存等功能。该芯片在接收端（RX）的灵敏度可达到-97dBm@1Mbps和-104dBm@125kbps（长距离模式）。它还支持可编程输出功率，最高可达+8dBm（在天线连接器处）。此外，它能够处理2Mbps、1Mbps、500kbps和125kbps等多种数据速率，并具有128个物理连接，内置 balun 和外部PA的支持。BluenRG核心协处理器用于蓝牙低能量的时间关键操作，基于DMA，同时包含一个2.4GHz的专有射频驱动器。这款芯片适用于需符合ETSI EN300328、EN300440、FCC CFR 47 Part 15和ARIB STD-T66等无线频率法规的系统。" "Bluenrg-lp在电源管理方面表现出色，拥有超低功耗特性。在SHUTDOWN模式下，电流消耗仅为10nA（1.8V电源）。在DEEP STOP模式下，如果使用外部LSE和BLE唤醒源，电流消耗为0.6uA（1.8V），而使用内部LSI和BLE唤醒源时，电流消耗为0.9uA（1.8V）。在传输（TX）峰值电流为4.3mA（@0dBm，3.3V），接收（RX）峰值电流为3.4mA（@灵敏度水平，3.3V）。" "该芯片搭载了一个高性能且超低功耗的Cortex-M0+ 32位微控制器，可在低功耗模式下运行，适合需要长时间电池寿命的应用。这款SoC设计考虑了能效与性能的平衡，是物联网设备、穿戴设备以及任何需要蓝牙连接且对功耗有严格要求的设备的理想选择。" "Bluenrg-lp数据手册详细介绍了其硬件接口、配置选项、软件开发环境以及各种功耗模式下的性能指标，对于设计和开发基于该芯片的系统至关重要。开发人员可以利用这些信息来优化其产品设计，确保其系统满足蓝牙5.2标准，并实现高效的电源管理。"

1.6.4 Power supply supervisor

The BlueNRG-LP device embeds several power voltage monitoring:

• Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR

threshold (typically 1.65 V)

• Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply voltage

(VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always enabled

• Power voltage detector (PVD): can be used to monitor the VDDIO (against a programmed threshold) or an

external analog input signal. When the feature is enabled and the PVD measures a voltage below the

comparator, an interrupt is generated (if unmasked)

1.7 Operating modes

Several operating modes are defined for the BlueNRG-LP:

• RUN mode

• DEEPSTOP mode

• SHUTDOWN mode

Table 2. Relationship between the low power modes and functional blocks

Mode SHUTDOWN DEEPSTOP IDLE RUN

CPU OFF OFF OFF ON

Flash OFF OFF ON ON

RAM OFF ON/OFF granularity 16 kB ON/OFF ON/OFF

Radio OFF OFF ON/OFF ON/OFF

Supply system OFF OFF ON ( DC-DC ON/OFF) ON ( DC-DC ON/OFF)

HS clock OFF OFF ON ON

LS clock OFF ON/OFF ON ON

Peripherals OFF OFF ON/OFF ON/OFF

Wake-on RTC OFF ON/OFF ON/OFF NA

Wake-on GPIOs OFF ON/OFF ON/OFF NA

Wake-on reset pin ON ON ON NA

1.7.1 RUN mode

In RUN mode the BlueNRG-LP is fully operational:

• All interfaces are active

• The internal power supplies are active

• The system clock and the bus clock are running

• The CPU core and the radio can be used

The power consumption may be reduced by gating the clock of the unused peripherals.

1.7.2 DEEPSTOP mode

The DEEPSTOP is the only low power mode of the BlueNRG-LP allowing the restart from a saved context

environment and the application at wake-up to go on running.

The conditions to enter the DEEPSTOP mode are:

• The radio is sleeping (no radio activity)

• The CPU is sleeping (WFI with SLEEPDEEP bit activated)

• No unmasked wake-up sources are active

• The low power mode selection (LPMS) bit of the power controller unit is 0 (default)

BlueNRG-LP

Operating modes

DS13282 - Rev 2

page 12/72

In DEEPSTOP mode:

• The system and the bus clocks are stopped

• Only the essential digital power domain is ON and supplied at 1.0 V

• The bank RAM0 is kept in retention

• The other banks of RAM can be in retention or not, depending on the software configuration

• The low speed clock can be running or stopped, depending on the software configuration:

– ON or OFF

– Sourced by LSE or by LSI

• The RTC and the IWDG stay active, if enabled and the low speed clock is ON

• The radio wake-up block, including its timer, stay active (if enabled and the low speed clock is ON)

• Eight I/Os (PA4/ PA5/ PA6/ PA7/ PA8/ PA9/ PA10/ PA11) can be in output driving:

– A static low or high level

– The low speed clock

– The RTC output

Possible wake-up sources are:

• The radio block is able to generate two events to wake up the system through its embedded wake-up timer

running on low speed clock:

– Radio wake-up time is reached

– CPU host wake-up time is reached

• The RTC can generate a wake-up event

• The IWDG can generate a reset event

• Up to 28 GPIOs are able to wake up the system (PA0 to PA15 and PB0 to PB11)

At the wake-up, all the hardware resources located in the digital power domain that are OFF during the

DEEPSTOP mode, are reset. The CPU reboots. The wake-up reason is visible in the register of the power

controller.

1.7.3 SHUTDOWN mode

The SHUTDOWN mode is the least power consuming mode.

The conditions to enter SHUTDOWN mode are the same conditions needed to enter DEEPSTOP mode except

that the LPMS bit of the power controller unit is 1.

In SHUTDOWN mode, the BlueNRG-LP is in ultra-low power consumption: all voltage regulators, clocks and the

RF interface are not powered. The BlueNRG-LP can enter shutdown mode by internal software sequence. The

only way to exit shutdown mode is by asserting and deasserting the RSTN pin.

In SHUTDOWN mode:

• The system is powered down as both the regulators are OFF

• The VDDIO power domain is ON

• All the clocks are OFF, LSI and LSE are OFF

• The I/Os pull-up and pull-down can be controlled during SHUTDOWN mode, depending on the software

configuration

• The only wake-up source is a low pulse on the RSTN pin

The exit from SHUTDOWN is similar to a POR startup. The PDR feature can be enabled or disabled during

SHUTDOWN.

1.8 Reset management

The BlueNRG-LP offers two different resets:

• The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and

corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset

impacts all resources of the BlueNRG-LP. The exit from SHUTDOWN mode is equivalent to a POR and thus

generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a

threshold value or when the regulator does not provide the target voltage.

BlueNRG-LP

Reset management

DS13282 - Rev 2

page 13/72

• The PADRESETn (system reset): this reset is built through several sources:

– PORESETn

– Reset due to the watchdog

The BlueNRG-LP device embeds a watchdog timer, which may be used to recover from software

crashes

– Reset due to CPU Lockup

The Cortex-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an

unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex-M0+

– Software system reset

The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets

the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system

reset request through the AIRCR can also be done by the embedded software (into the hardfault

handler for instance)

– Reset from the RSTN external pin

The RSTN pin toggles to inform that a reset has occurred

This PADRESETn resets all resources of the BlueNRG-LP, except:

• Debug features

• Flash controller key management

• RTC timer

• Power controller unit

• Part of the RCC registers

The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case

of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.

1.9

Clock management

Three different clock sources may be used to drive the system clock of the BlueNRG-LP:

• HSI: high speed internal 64 MHz RC oscillator

• PLL64M: 64 MHz PLL clock

• HSE: high speed 32 MHz external crystal

The BlueNRG-LP has also a low speed clock tree used by some timers in the radio, RTC and IWDG.

Four different clock sources can be used for this low speed clock tree:

• Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and 49

kHz depending on the sample

• Low speed external (LSE) from:

– An external crystal 32.768 kHz

– A single-ended 32.738 kHz input signal

• A 32 kHz clock (CLK_16 MHz/512 in Figure 6. Clock tree) obtained by dividing HSI or HSE. In this case, the

slow clock is not available in DEEPSTOP low power mode

• LSI_LPMU: 32 kHz clock used by the low power management unit (LPMU) analog block.

By default, after a system reset, all low speed sources are OFF.

Both the activation and the selection of the slow clock are relevant during the DEEPSTOP mode and at wakeup

as slow clock generates a clock for the timers involved in wake-up event generation.

The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock

output by this block can be:

• A non-accurate clock when no external XO provides an input clock to this block (HSI)

• An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)

This fast clock source is used to generate all the fast clock of the device through dividers. After reset, the

CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and peripherals).

This fast clock source is also used to generate several internal fast clocks in the system:

• Always 32 MHz requested by a few peripherals like the radio

BlueNRG-LP

Clock management

DS13282 - Rev 2

page 14/72

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