JEDEC标准21-C：LPDDR3和LPDDR4 SPD规范

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"JEDEC标准No.21-C主要涵盖了串行存在检测（SPD）协议，特别是针对LPDDR3和LPDDR4低功耗双数据速率同步动态随机存取存储器（SDRAM）模块。这个标准由JEDEC固态技术协会制定，用于定义LP-DIMM（低功耗双列直插内存模块）的版本1.0规范。文档的目的是详细说明SPD值，这些值在模块的特定功能中被引用。" JEDEC标准No.21-C中的Annex M部分专门讨论了LPDDR3和LPDDR4 SDRAM模块的SPD，这是一种通信协议，允许系统读取内存模块上的配置信息，如时序参数、电压等级和制造商信息。这些信息对于系统能够正确初始化和优化内存设置至关重要。文档中提到的“Release 25”可能指的是该标准的第25次修订或发布，这通常意味着对标准进行了更新和改进，以适应技术的发展。LPDDR3和LPDDR4是低功耗内存的标准，广泛应用于移动设备和节能型计算机系统，因为它们在保持高性能的同时，显著降低了功耗。标准指出，所有未使用的条目应编码为0x00，而在定义的字节中，除非特别说明，未使用的位也应编码为0。这意味着SPD数据结构有严格的填充规则，以确保正确性和一致性。 SPD中的时序参数代表模块（包括所有DRAM和辅助设备）在最低支持供电电压下的操作，此电压由SPD字节11定义。这些参数的有效范围是从tCKAVG最小值到tCKAVG最大值，具体由SPD的字节18和19确定。tCKAVG是时钟周期的平均时间，是衡量内存性能的关键指标。为了适应不同工作条件和未来的技术升级，SPD标准允许有一定的灵活性。例如，它可能包含预留字段或可扩展的结构，使得新特性可以在不改变基础标准的情况下得以添加。 JEDEC Standard No. 21-C的Annex M提供了关于如何定义和使用LPDDR3和LPDDR4 SDRAM模块SPD信息的详细指南，对于硬件设计师、系统架构师和内存制造商来说，这是一个至关重要的参考资源，确保了内存模块与系统的兼容性和性能。

Release 25

JEDEC Standard No. 21-C

Page 4.1.2.M-1 – 6

The DRAM Device Type byte defines an interface compatibility family more than it identifies a specific memory device. For

example, where an LP memory module may expose the devices directly to the edge connector contacts, a load reduced memory

module presents the interfaces of registering clock drivers and data buffers to the edge connector contacts. There may be memory

modules with completely different devices, such as non-volatile memories, however these may define themselves as a base memory

type such as LPDDR SDRAM for interface compatibility with the memory controller. The memory controller must be aware of its

capabilities when parsing the SPD.

3.1.4 Byte 3 (0x003): Key Byte / Module Type

This byte, shown in Table 8, is a Key Byte used to index the module specific section of the SPD from bytes 128~255 and bytes

256~319. Byte 3 bits 3~0 identifies the SDRAM memory module type.

Bits 7~4 identifies the architecture of the secondary memory type, if any, present on the module in addition to the base DRAM. These

secondary hybrid architectures may apply to any Base Module Type. The index in bits 7~4 is used to index the hybrid memory

architecture specific section of the SPD from bytes 256~319.

System software supporting hybrid memory modules should parse the DRAM attributes per the Base Module Type and combine the

indexed information per the Hybrid Memory Type to determine the combined memory module capabilities.

Where base memory parameters apply to this class of hybrid module, these will be documented with those bytes in the base section.

Extended parameters are encoded in SPD bytes 256~319. When a module has no base memory present, the special coding 1111 shall

be used in bits 3~0 of byte 2.

Examples:

0x07 = LP-DIMM, no hybrid memory present

0x0E = soldered down memory, no hybrid memory present

NOTE LP-DIMMs incorporate two independent 32 bit channels per module. Non-DIMM solutions such as solder down applications may incorporate

any number of channels, yet use SPD codes to simplify software configuration for the application.

Table 8 — Byte 3 (0x003): Key Byte / Module Type

Bit 7 Bits 6~4 Bits 3~0

Hybrid Hybrid Media Base Module Type

0 = Not hybrid

(Module is DRAM only)

1 = Hybrid module

(See bits 6~4 for hybrid type)

Bits [6, 5, 4]:

000 = Not hybrid

001 = Reserved

All other codes reserved

Bits [3, 2, 1, 0]:

0000 = Extended DIMM type, see byte 15 (0x00F)

0111 = LP-DIMM

1110 = Non-DIMM Solution

1111 = Reserved

Base Module Type Definitions:

LP-DIMM: Low Power Unbuffered Small Outline Dual In-Line Memory Module, 64-bit data bus

Non-DIMM Solution: Used to define when the SDRAM Devices may be placed on the main board rather than on a

module.

NOTE No hybrid LPDDR compatible modules are defined at this time.

3.1 General Configuration Section: Bytes 0~127 (0x000~0x07F) (Cont’d)

3.1.3 Byte 2 (0x002): Key Byte / DRAM Device Type (Cont’d)

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