W25Q32JVZPIQ：3V 32M位SPI闪存模块规格与功能概述

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W25Q32JVZPIQ是一款专为工业和工业加强级设计的3V 32M位串行闪存存储器，它支持双通道和四通道SPI接口。该产品发布日期为2018年3月27日，修订至版本G。这款内存模块提供了多种封装形式，包括SOIC 150/208-mil、VSOP 208-mil、WSON 6x5-mm/8x6-mm、XSON 4x4-mm、SOIC 300-mil、TFBGA 8x6-mm (5x5或6x4球栅阵列)以及PDIP 300-mil。产品的主要特性包括但不限于： 1. 通用描述：W25Q32JV提供串行数据传输，便于在不同应用场景下通过SPI接口进行高效通信。其双通道和四通道模式支持并行操作，提升数据读写速度。 2. 封装及引脚配置： - SOIC和VSOP封装具有特定的引脚布局和尺寸，如150/208-mil，用于简化电路板设计。 - WSON和XSON封装则适合紧凑型应用，分别为6x5-mm和4x4-mm尺寸。 - SOIC 300-mil封装适合对空间有更高要求的应用。 - TFBGA封装采用8x6-mm球栅阵列，提供5x5或6x4球排列，有助于提高集成度。 - PDIP 300-mil封装是传统的直插式封装，便于测试和调试。 3. 引脚功能：包括芯片选择（/CS）、串行数据输入/输出（DI, DO, IO0, IO1, IO2, IO3）、写保护（/WP）、保持信号（/HOLD）、时钟信号（CLK）和复位信号（/RESET）。这些引脚的精确定义有助于用户正确连接和操作设备。 4. 功能描述： - 标准SPI指令集：介绍如何通过SPI协议与W25Q32JV交互，包括读取、写入和命令发送等基本操作。 - 双通道和四通道SPI指令：展示了如何利用额外的数据线通道来实现更快速的数据传输。 - 软件和硬件重置：说明了如何通过软件或硬件方式来初始化和恢复闪存的正常工作状态。 W25Q32JVZPIQ是一款高性能且灵活的存储解决方案，适用于各种工业级应用，通过其不同的封装选项适应不同的系统需求，并提供丰富的接口选项和引脚功能，方便设计师根据项目需求进行选择和集成。对于从事嵌入式系统设计或者需要扩展闪存容量的工程师来说，这款产品具有很高的实用价值。

W25Q32JV

Publication Release Date: March 27, 2018

- 12 - Revision G

6.5 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern, the W25Q32JV

provides several means to protect the data from inadvertent writes.

Write Protect Features

 Device resets when VCC is below threshold

 Time delay write disable after Power-up

 Write enable/disable instructions and automatic write disable after erase or program

 Software and Hardware (/WP pin) write protection using Status Registers

 Additional Individual Block/Sector Locks for array protection

 Write Protection using Power-down instruction

 Lock Down write protection for Status Register until the next power-up

 One Time Program (OTP) write protection for array and Security Registers using Status Register

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q32JV will maintain a reset condition while VCC is below the

threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This

includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status

the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-

down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to

accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector

Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a

program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled

state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the

Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[2:0]) bits. These settings allow a

portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect

(/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status

write protection as all instructions are ignored except for the Release Power-down instruction.

The W25Q32JV also provides another Write Protect method using the Individual Block Locks. Each 64KB

block (except the top and bottom blocks, total of 62 blocks) and each 4KB sector within the top/bottom

blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the

corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program

commands issued to the corresponding sector or block will be ignored. When the device is powered on, all

Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An

“Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.

The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When

WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of

the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

W25Q32JV

- 13 -

7. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for W25Q32JV. The Read Status Register-1/2/3

instructions can be used to provide status on the availability of the flash memory array, whether the

device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock

status, Erase/Program Suspend status, and output driver strength. The Write Status Register instruction

can be used to configure the device write protection features, Quad SPI setting, Security Register OTP

locks, and output driver strength. Write access to the Status Register is controlled by the state of the non-

volatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI

operations.

7.1 Status Registers

Figure 4a. Status Register-1

Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or

Erase/Program Security Register instruction. During this time the device will ignore further instructions

except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE

in AC Characteristics). When the program, erase or write status/security register instruction has completed,

the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write

Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable

state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad

Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and

Program Security Register.

Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and

S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status

protected from Program and Erase instructions (see Status Register Memory Protection table). The factory

default setting for the Block Protection Bits is 0, none of the array protected.

SRP

SEC

WEL

BUSY

TOP/BOTTOM PROTECT

WRITE ENABLE LATCH

STATUS REGISTER PROTECT

SECTOR PROTECT

BLOCK PROTECT BITS

WRITE IN PROGRESS

(volatile/non-volatile)

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