"TI-PCA9515B.pdf: I2C缓冲器使用指南"
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更新于2024-03-12
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The TI-PCA9515B is a versatile I2C buffer designed to provide signal buffering and voltage level shifting for I2C communication between a master device (such as a processor) and multiple slave devices. This buffer, designated as PCA9515BSCL0SDA0SCL1SDA1GNDVCCEN, is capable of enhancing the signal integrity and driving capability of the I2C bus, ensuring reliable data transmission in various applications.
With its dual I2C channels, this buffer is capable of connecting two separate I2C buses, allowing for efficient communication between multiple devices without signal interference. The buffer operates within a voltage range of VCC to VCC, providing flexibility in design and compatibility with various power supply configurations.
Additionally, the PCA9515B features an enable pin (EN) that allows for the easy control of the buffer's operation, enabling users to effectively manage power consumption and device communication. This further enhances the versatility and efficiency of the buffer in a wide range of applications.
Overall, the TI-PCA9515B I2C buffer is a reliable and flexible solution for enhancing I2C communication in complex systems, providing signal buffering, voltage level shifting, and efficient signal management for seamless data transmission between master and slave devices. Its robust design, high performance, and ease of use make it an ideal choice for applications requiring reliable and high-speed I2C communication.
5
PCA9515B
www.ti.com.cn
ZHCS780B –MARCH 2012–REVISED MARCH 2016
Copyright © 2012–2016, Texas Instruments Incorporated
(1) All typical values are at nominal supply voltage (V
CC
= 2.5 V or 3.3 V) and T
A
= 25°C.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= –18 mA 2.3 V to 3.6 V –1.2 V
V
OL
Low-level output voltage
SDAx,
SCLx
I
OL
= 20 μA or 6 mA 2.3 V to 3.6 V 0.47 0.52 0.6 V
V
OL
– V
ILc
Low-level input voltage below
low-level output voltage
SDAx,
SCLx
guaranteed by design 2.3 V to 3.6 V 120 mV
I
CC
Quiescent supply current
Both channels high,
SDAx = SCLx = V
CC
2.7 V 0.5 3
mA
3.6 V 0.5 3
Both channels low,
SDA0 = SCL0 = GND and
SDA1 = SCL1 = open; or
SDA0 = SCL0 = open and
SDA1 = SCL1 = GND
2.7 V 1 4
3.6 V 1 4
In contention,
SDAx = SCLx = GND
2.7 V 1 4
3.6 V 1 4
I
I
Input current
SDAx,
SCLx
V
I
= 3.6 V
2.3 V to 3.6 V
±1
μA
V
I
= 0.2 V 3
EN
V
I
= V
CC
±1
V
I
= 0.2 V –10 –20
I
off
Leakage current
SDAx,
SCLx
V
I
= 3.6 V
EN = L or H 0 V
0.5
μA
V
I
= GND 0.5
I
I(ramp)
Leakage current during
power up
SDAx,
SCLx
V
I
= 3.6 V EN = L or H 0 V to 2.3 V 1 μA
C
in
Input capacitance
EN
V
I
= 3 V or GND
3.3 V 7 9
pF
SDAx,
SCLx
EN = H 3.3 V 7 9
6.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
V
CC
MIN MAX UNIT
t
su
Setup time, EN↑ before Start condition
2.5 V ± 0.2 V 100
ns
3.3 V ± 0.3 V 100
t
h
Hold time, EN↓ after Stop condition
2.5 V ± 0.2 V 130
ns
3.3 V ± 0.3 V 100
(1) All typical values are at nominal supply voltage (V
CC
= 2.5 V or 3.3 V) and T
A
= 25°C.
(2) Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
6.7 Switching Characteristics
over recommended operating free-air temperature range, C
L
≤ 100 pF (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
MIN TYP
(1)
MAX UNIT
t
PZL
Propagation delay time
(2)
SDA0, SCL0 or
SDA1, SCL1
SDA1, SCL1 or
SDA0, SCL0
2.5 V ± 0.2 V 45 82 130
ns
3.3 V ± 0.3 V 45 68 120
t
PLZ
2.5 V ± 0.2 V 33 113 190
3.3 V ± 0.3 V 33 102 180
t
tHL
Output transition time
(2)
(SDAx, SCLx)
80% 20%
2.5 V ± 0.2 V 57
ns
3.3 V ± 0.3 V 58
t
tLH
20% 80%
2.5 V ± 0.2 V 148
3.3 V ± 0.3 V 147
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