Rabaey、Chandrakasan & Nikolic的数字集成电路设计指南（2nd版）概述

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《数字集成电路：设计视角（第二版）》是由Jan M. Rabaey、Anantha Chandrakasan和Borivoje Nikolic合著，由Pearson出版社于2003年出版的一本经典教材。该书主要探讨了数字集成电路的设计原理，重点涵盖了从历史背景、设计挑战到制造工艺、器件选择以及布局技术等多个关键领域。在本书的开篇，第一章"Introduction"（引言）中，作者为读者提供了一个历史性的视角，介绍了数字集成电路的发展历程，强调了设计中的关键问题，如成本、功能与可靠性、性能以及能耗。这一章概述了衡量一个数字设计质量的四个主要指标，并引导读者深入探究相关话题。第二章"THE MANUFACTURING PROCESS"（制造过程）详细解析了CMOS集成电路的制造流程，包括硅晶圆的使用、光刻技术、基本步骤以及简化的过程流程。此外，章节还讨论了设计者与工艺工程师之间的合同——设计规则，以及集成电路的封装技术，包括材料、层次结构和热管理问题。作者还借此机会展望了工艺技术的发展趋势，包括短期和长期的技术革新。第三章"The Devices"（器件）着重于介绍集成电路中的基本元件，包括二极管、三极管、场效应晶体管等，这些是构建数字电路的基础。读者将学习如何选择合适的器件来实现特定的电路功能，并理解这些器件如何影响电路性能和能耗。设计方法论插件A"IC LAYOUT"（集成电路布局）在书中占据重要地位，这一部分会深入讲解电路设计的布局技巧和策略，使读者掌握如何将电路原理图转化为实际的物理布局，以优化信号完整性、噪声抑制和功耗控制。《数字集成电路：设计视角（第二版）》为读者提供了一个全面而深入的数字电路设计指南，涵盖了从基础理论到实践应用的各个环节，对于电子工程专业学生和从业者来说是一本不可或缺的参考书。然而，值得注意的是，由于缺失了第11章和第12章，这部分内容可能无法涵盖，读者需要寻找其他资料来补充完整的设计流程和高级主题。

14 INTRODUCTION Chapter 1

Designers have, therefore, increasingly adhered to rigid design methodologies and strate-

gies that are more amenable to design automation. The impact of this approach is apparent

from the layout of one of the later Intel microprocessors, the Pentium® 4, shown in Figure

1.5b. Instead of the individualized approach of the earlier designs, a circuit is constructed

in a hierarchical way: a processor is a collection of modules, each of which consists of a

number of cells on its own. Cells are reused as much as possible to reduce the design effort

and to enhance the chances for a first-time-right implementation. The fact that this hierar-

chical approach is at all possible is the key ingredient for the success of digital circuit

design and also explains why, for instance, very large scale analog design has never

caught on.

The obvious next question is why such an approach is feasible in the digital world

and not (or to a lesser degree) in analog designs. The crucial concept here, and the most

important one in dealing with the complexity issue, is abstraction. At each design level,

the internal details of a complex module can be abstracted away and replaced by a black

box view or model. This model contains virtually all the information needed to deal with

the block at the next level of hierarchy. For instance, once a designer has implemented a

multiplier module, its performance can be defined very accurately and can be captured in a

model. The performance of this multiplier is in general only marginally influenced by the

way it is utilized in a larger system. For all purposes, it can hence be considered a black

box with known characteristics. As there exists no compelling need for the system

designer to look inside this box, design complexity is substantially reduced. The impact of

this divide and conquer approach is dramatic. Instead of having to deal with a myriad of

elements, the designer has to consider only a handful of components, each of which are

characterized in performance and cost by a small number of parameters.

This is analogous to a software designer using a library of software routines such as

input/output drivers. Someone writing a large program does not bother to look inside those

library routines. The only thing he cares about is the intended result of calling one of those

modules. Imagine what writing software programs would be like if one had to fetch every

bit individually from the disk and ensure its correctness instead of relying on handy “file

open” and “get string” operators.

Figure 1.4 Microprocessor performance

trends at the beginning of the 21st century.

Pentium ® proc

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Pentium ® proc

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chapter1.fm Page 14 Friday, January 18, 2002 8:58 AM

Section 1.2 Issues in Digital Integrated Circuit Design 17

instance, apparent in the layout of the Pentium ® 4 processor (Figure 1.5b). The integer

and floating-point unit, just to name a few, contain large sections designed using the so-

called standard cell approach. In this approach, logic gates are placed in rows of cells of

equal height and interconnected using routing channels. The layout of such a block can be

generated automatically given that a library of cells is available.

The preceding analysis demonstrates that design automation and modular design

practices have effectively addressed some of the complexity issues incurred in contempo-

rary digital design. This leads to the following pertinent question. If design automation

solves all our design problems, why should we be concerned with digital circuit design at

all? Will the next-generation digital designer ever have to worry about transistors or para-

sitics, or is the smallest design entity he will ever consider the gate and the module?

The truth is that the reality is more complex, and various reasons exist as to why an

insight into digital circuits and their intricacies will still be an important asset for a long

time to come.

• First of all, someone still has to design and implement the module libraries. Semi-

conductor technologies continue to advance from year to year. Until one has devel-

oped a fool-proof approach towards “porting” a cell from one technology to another,

each change in technology—which happens approximately every two

years—requires a redesign of the library.

• Creating an adequate model of a cell or module requires an in-depth understanding

of its internal operation. For instance, to identify the dominant performance parame-

ters of a given design, one has to recognize the critical timing path first.

• The library-based approach works fine when the design constraints (speed, cost or

power) are not stringent. This is the case for a large number of application-specific

designs, where the main goal is to provide a more integrated system solution, and

performance requirements are easily within the capabilities of the technology.

Unfortunately for a large number of other products such as microprocessors, success

hinges on high performance, and designers therefore tend to push technology to its

limits. At that point, the hierarchical approach tends to become somewhat less

attractive. To resort to our previous analogy to software methodologies, a program-

mer tends to “customize” software routines when execution speed is crucial; com-

pilers—or design tools—are not yet to the level of what human sweat or ingenuity

can deliver.

• Even more important is the observation that the abstraction-based approach is only

correct to a certain degree. The performance of, for instance, an adder can be sub-

stantially influenced by the way it is connected to its environment. The interconnec-

tion wires themselves contribute to delay as they introduce parasitic capacitances,

resistances and even inductances. The impact of the interconnect parasitics is bound

to increase in the years to come with the scaling of the technology.

• Scaling tends to emphasize some other deficiencies of the abstraction-based model.

Some design entities tend to be global or external (to resort anew to the software

analogy). Examples of global factors are the clock signals, used for synchronization

in a digital design, and the supply lines. Increasing the size of a digital design has a

chapter1.fm Page 17 Friday, January 18, 2002 8:58 AM

18 INTRODUCTION Chapter 1

profound effect on these global signals. For instance, connecting more cells to a sup-

ply line can cause a voltage drop over the wire, which, in its turn, can slow down all

the connected cells. Issues such as clock distribution, circuit synchronization, and

supply-voltage distribution are becoming more and more critical. Coping with them

requires a profound understanding of the intricacies of digital circuit design.

• Another impact of technology evolution is that new design issues and constraints

tend to emerge over time. A typical example of this is the periodical reemergence of

power dissipation as a constraining factor, as was already illustrated in the historical

overview. Another example is the changing ratio between device and interconnect

parasitics. To cope with these unforeseen factors, one must at least be able to model

and analyze their impact, requiring once again a profound insight into circuit topol-

ogy and behavior.

• Finally, when things can go wrong, they do. A fabricated circuit does not always

exhibit the exact waveforms one might expect from advance simulations. Deviations

can be caused by variations in the fabrication process parameters, or by the induc-

tance of the package, or by a badly modeled clock signal. Troubleshooting a design

requires circuit expertise.

For all the above reasons, it is my belief that an in-depth knowledge of digital circuit

design techniques and approaches is an essential asset for a digital-system designer. Even

though she might not have to deal with the details of the circuit on a daily basis, the under-

standing will help her to cope with unexpected circumstances and to determine the domi-

nant effects when analyzing a design.

Example 1.1 Clocks Defy Hierarchy

To illustrate some of the issues raised above, let us examine the impact of deficiencies in one

of the most important global signals in a design, the clock. The function of the clock signal in

a digital design is to order the multitude of events happening in the circuit. This task can be

compared to the function of a traffic light that determines which cars are allowed to move. It

also makes sure that all operations are completed before the next one starts—a traffic light

should be green long enough to allow a car or a pedestrian to cross the road. Under ideal cir-

cumstances, the clock signal is a periodic step waveform with transitions synchronized

throughout the designed circuit (Figure 1.7a). In light of our analogy, changes in the traffic

lights should be synchronized to maximize throughput while avoiding accidents. The impor-

tance of the clock alignment concept is illustrated with the example of two cascaded registers,

both operating on the rising edge of the clock φ (Figure 1.7b). Under normal operating condi-

tions, the input In gets sampled into the first register on the rising edge of φ and appears at the

output exactly one clock period later. This is confirmed by the simulations shown in Figure

1.8c (signal Out).

Due to delays associated with routing the clock wires, it may happen that the clocks

become misaligned with respect to each other. As a result, the registers are interpreting time

indicated by the clock signal differently. Consider the case that the clock signal for the second

postpone the sampling of the input of the second register. If the time it takes to propagate the

output of the first register to the input of the second is smaller than the clock delay, the latter

will sample the wrong value. This causes the output to change prematurely, as clearly illus-

trated in the simulation, where the signal Out′ goes high at the first rising edge of φ′ instead of

chapter1.fm Page 18 Friday, January 18, 2002 8:58 AM

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