Teknovus TK3723: Dual Turbo-Ethernet PON MAC Traffic Manager

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"TK3723 Data Sheet 是一份关于 Teknovus 公司的 Dual Turbo-EPO NTM（网络交通管理器）芯片的初步技术规格文档。这份文档仅供具有非披露协议（NDA）的人员查看。TK3723 设计用于光线路终端（OLT），提供了两个符合 IEEE 802.3ah 标准的以太网无源光网络（EPON）MAC 控制器，支持 2.5Gbps 和 1.25Gbps 的下行速率选项，以及每个 PON 通道上的 1.25Gbps 上行速率。此外，它还包含两个符合 IEEE 802.3z 的千兆以太网 MAC 控制器，支持 MII、GMII 和 TBI 接口。" 本文档的特点包括： 1. **双 IEEE 802.3ah EPON MAC 控制器**：芯片集成了两个 EPON MAC 控制器，可处理高速的上行和下行数据流，适应不同的网络速度需求。 2. **动态带宽分配（DBA）**：硬件级别的 DBA 功能允许动态调整带宽分配，以优化网络资源使用，提高服务质量和效率。 3. **嵌入式 ARM9 处理器的系统解决方案**：内置的 ARM9 处理器可以运行固件，提供更高效的操作和控制功能。 4. **IEEE 802.3ah OAM 支持**：实现在线路维护和故障检测方面的操作、管理和维护功能，确保网络的稳定运行。 5. **PON 接口的 IEEE 802.3ah 前向纠错**：增强数据传输的可靠性，通过纠正错误来减少数据丢失。 6. **IEEE 802.1D 桥接**：提供 8K MAC 地址学习和老化功能，增强了本地接口的连接管理。 7. **802.1p 优先级队列**：支持每个 LLID（逻辑链路标识）的四个优先级队列，优化了服务质量（QoS）。 8. **802.1Q VLAN 映射**：将 VLAN 映射到 LLID，实现灵活的网络隔离和管理。 9. **双向 LLID 支持**：每个 PON 接口支持 256 个双向（上下行）LLID 和 128 个下行多播 LLID，增强多用户服务。 10. **客户级安全**：使用 AES-128 加密或 Triple Churning (CTC) 算法对每个 LLID 下游数据进行加密，保障数据安全。 11. **线速层二处理**：芯片能够实现全速的二层处理，确保在网络流量大的情况下，数据传输不受影响。 TK3723 芯片是专为高性能 EPON 网络设计的，它提供了一整套集成化的网络管理和安全特性，适用于构建高效、可靠的光接入网络。其丰富的功能和高带宽能力使其成为 OLT 设备的理想选择。

TK3723 Data Sheet – Preliminar

Dual Turbo-EPON

MAC Traffic Manager for OLT

Page 15 of 89 Rev 0.23

Teknovus Confidential - View Under NDA Only

within operating range

outside operating range - above saturation level

Optical Power

[dBm]

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

Receiver not FEC-ready Receiver FEC-ready

outside operating range – below noise level

SD hysteresis

FEC Gain

(SD function must prevent entering this region)

Figure 11. FEC and Squelch Regions for typical APD receiver

The FEC coding is effective on bit error rates (BER) down to 1E-4. The loss of signal level should be set to an

optical power level that corresponds to a BER of 1E-4. This is typically adjusted through a resistor setting

connected to the post amp.

The timing of the squelch circuit is important as well. The threshold should be adjusted such that the squelch is

activated at the end of an upstream burst prior to noise being output.

Teknovus does not recommend disabling the squelch function, even when FEC is used

. The optical noise

between burst at BER rates higher than 1E-4 has been shown to result in packet loss and deregistration on the

PON.

1.3 Dynamic Bandwidth Allocation Control (DBA)

The Dynamic Bandwidth Allocation (DBA) modules schedule upstream traffic on the PON (see Figure 2.

DBA schedules two major types of traffic:

• Solicited – Shaped, scheduled grants which dynamically respond to the amount of upstream data

reported by ONUs, and to the amount of space available in the destination queue

• TDM – High priority, unsolicited, fixed-period grants used to transport traffic requiring low latency.

TK3723 Data Sheet – Preliminar

Dual Turbo-EPON

MAC Traffic Manager for OLT

Page 16 of 89 Rev 0.23

Teknovus Confidential - View Under NDA Only

For Solicited traffic, DBA contains a Shaper/Scheduler that supports two Shaping elements and two Scheduling

elements per LLID for true minimum- and maximum-rate PON scheduling. The Shaper enforces rate and burst

size parameters for each LLID, and the Scheduler ensures that the PON bandwidth is divided into the desired

proportions. The Shaper supports rates between 256 Kbps and 1 Gbps. The Scheduler is a hierarchical weighted

round-robin (HWRR) design, with 8 priority levels and drop-down reservations between priority levels.

A Polling engine in DBA supports Solicited granting. The polling engine allows the user to configure regular

report-only grants to each solicited LLID. These grants alert DBA to the presence of ONU data that must be sent

upstream. The polling interval is programmable to allow tradeoffs between latency and bandwidth overhead.

A TDM grant engine in DBA generates high-priority grants at regular intervals. The TDM engine supports 64

“channels” of TDM grants. Each channel can be assigned to an LLID and is programmable for grant length and

grant interval.

EPON uses a nominal PON loop time of 250us. The TK3723 DBA supports loop times between 150us and 750us.

1.4 IEEE 802.3z Gigabit Ethernet MACs

The two IEEE 802.3z Gigabit Ethernet MACs make up the Network-side interface of the TK3723. They support

full duplex operation at 100 or 1000 Mbps, auto-negotiation and 802.3x Flow Control.

The Gigabit MACs connect to external 100/1000 Mbps Ethernet PHY devices via GMII or TBI.

The Gigabit MACs collect statistics to support RMON Level 2 requirements.

1.5 Lookup Engines (LUEs)

The Lookup Engines (LUEs) are used to modify frames and switch frames between queues, LLIDs, and VLANs.

The LUEs support static bridging, learning bridging, and VLAN bridging architectures. A total of 16K MAC

addresses are supported.

• When configured for static bridging in the downstream direction, MAC addresses can be mapped to

the 256 possible LLIDs. Additional packet fields, such as IP DiffServ and protocol, can be used to

separate traffic into different LLIDs or queues. In this configuration, the Ethernet LUE would be

configured only to parse OAM traffic to the ARM processor.

• When configured for learning bridging, the downstream EPON LUEs look up a frame’s Destination

Address (DA) in the MAC Address table. They then set a destination for the frame. Along with lookups

on other fields, the destination lookup results in determining a queue and an LLID for the frame. In

upstream bridging mode, the LUEs search for an SA. If the SA is not found, it is added to the MAC

address table. The new Address allows downstream frames (with a DA matching the recently learned

SA) to be forwarded to the appropriate LLID. Address aging times can be provisioned through the Host

Interface. They can take on values of the form 2^N * 8.75ms for N from 0 to 15, and are accurate to

within 12.5% of the provisioned value.

• When configured for VLAN bridging, the downstream EPON Lookup Engines map the VLAN tag to an

LLID and a downstream queue. The VLAN tag is removed from the packet before being queued for the

downstream. The upstream engine maps the upstream LLID to a VLAN tag. The LLID is removed and

the appropriate VLAN tag is inserted.

The Lookup Engines process all frames at full line rate, including continuous minimum-sized frames. The LUE

tables are stored in dedicated internal SRAM.

TK3723 Data Sheet – Preliminar

Dual Turbo-EPON

MAC Traffic Manager for OLT

Page 17 of 89 Rev 0.23

Teknovus Confidential - View Under NDA Only

1.6 Packet Buffering (FIFOs)

External DDRII DRAM memory is used for packet buffering (FIFOs). The TK3723 supports 2048 packet FIFOs,

512 to each of the four FIFO destinations (2 EPON interfaces, 2 Gigabit Ethernet interfaces). Each FIFO has a

programmable size up to 1 MB, with a granularity of 4 KB.

Packets are stored in two banks of DDRII DRAM memory. Each port (channel) uses two 512 Mbit, 16-bit-wide

DDRII DRAM chips to implement a 32-bit wide, 128 MB memory array. DDRII DRAM memories are clocked at

125MHz. Both DDRII DRAM memory chips forming a single 32-bit wide data bus must have identical AC

characteristics. Each DDRII DRAM memory chip must support following features/parameters:

• 32M x 16-bit capacity (512Mb, 2 per port)

• Operating Frequency = 125MHz (DDR)

• Burst Type = Sequential

• Burst Length = 8

• CAS Latency (CL) = 3

• Write Recovery (WR) = 2

• Additive CAS Latency (AL) = 0

• On-Die Termination (ODT) = 75Ω

• t

= +/-800ps

• t

RCD

= 16ns

• t

= 16ns

• t

= 60ns

• t

RFC

= 105ns

• Refresh Rate = 7.8125us (8192 refresh cycles every 64ms; commercial).

1.6.1 DDRII Interfaces PCB Layout Guidelines

TK3723

Channel 2

Channel 1

VTT = 0.9V

DDR2_P1_A[12..0]/BA[2..0]

DDRII

(port 1, chip 0)

DDR2_P1_DQ1_[15..0]

DDR2_P1_CLK0_P/N

DDR2_P1_RAS/CAS/CS/WE_N

VTT

(4x)

VTT

(2x)

DDRII

(port 1, chip 1)

DDR2_P1_CLK1_P/N

DDR2_P1_DQ0_[15..0]

VTT

(2x)

DDR2_P1_ODT/CKE

DDR2_P1_U/LDQS0_P/N

DDR2_P1_U/LDQS1_P/N

must be 40mm longer than

DDR2_P1_CLK1_P/N

must be 40mm longer than

DDR2_P1_CLK0_P/N

DDR2_P2_A[12..0]/BA[2..0]

DDRII

(port 2, chip 0)

DDR2_P2_DQ1_[15..0]

DDR2_P2_CLK0_P/N

DDR2_P2_RAS/CAS/CS/WE_N

VTT

(4x)

VTT

(2x)

DDRII

(port 2, chip 1)

DDR2_P2_CLK1_P/N

DDR2_P2_DQ0_[15..0]

VTT

(2x)

DDR2_P2_ODT/CKE

DDR2_P2_U/LDQS0_P/N

DDR2_P2_U/LDQS1_P/N

must be 40mm longer than

DDR2_P2_CLK1_P/N

must be 40mm longer than

DDR2_P2_CLK0_P/N

VTT

(16x)

VTT

(16x)

separate bias resistors

for CLK signals

separate bias resistors

for CLK signals

differential pairs (Z

diff

= 80Ω)

single-ended signals (Zo = 50Ω)

4.7K

(2x)

4.7K

(2x)

Figure 12. TK3723 DDRII Interfaces

Following are PCB layout guidelines for DDRII interfaces (applicable to each port x independently):

• Single-ended DDR2_Px_DQ0/1_[15..0] data signals should be matched in length to +/-5mm and be

shorter than 50mm (per port i.e. to both memory chips)

• Differential DDR2_Px_CLK0/1_P/N signal should be matched within the differential pair to +/-1mm, and

should be matched in length with DDR2_Px_DQ0/1_[15..0] (max 50mm; +/-5mm)

TK3723 Data Sheet – Preliminar

Dual Turbo-EPON

MAC Traffic Manager for OLT

Page 18 of 89 Rev 0.23

Teknovus Confidential - View Under NDA Only

• All DDR2_Px_U/LDQS0/1_P/N strobe signals should be matched within the differential pair to +/-1mm

and must be longer by 40mm

than corresponding DDR2_Px_CLK0/1_P/N clock signals pairs (see Table

34 for AC timing details)

• DDR2_Px_A[12..0], DDR2_Px_BA[1..0], DDR2_Px_CS_N, DDR2_Px_WE_N, DDR2_Px_RAS_N,

DDR2_Px_CAS_N, DDR2_Px_L/UDM0/1 signals should be matched in length to +/-5mm and be shorter

than 75mm

• All DDRII signals must be impedance controlled. Single-ended signals must have impedance of 50Ω

(+/-10%), and differential signals 80Ω (+/-10%). Differential signals are recommended to be “loosely

coupled” to prevent excessive impedance variations due to PCB manufacturing variability

• Use biasing/termination and decoupling methods as implemented on Teknovus TK3723 evaluation

boards.

1.7 Shapers/Schedulers

The Shaper/Scheduler blocks schedule traffic as follows:

• Downstream from the FIFO queues to the EPON MACs (EPON Shapers/Schedulers)

• Upstream from the FIFO queues to the Network-side Gigabit Ethernet MACs (Ethernet

Shapers/Schedulers).

Each Shaper/Scheduler supports two Shaping elements and two Scheduling elements per FIFO queue, for true

minimum and maximum-rate scheduling.

The Shaper enforces rate and burst-size parameters for each FIFO. Rates are configurable per-queue between

256 Kbps and 1 Gbps. Burst sizes are set in 1 KB increments between 1 KB and 256 KB.

The Scheduler ensures that the channel bandwidth is divided into the desired proportions. The Scheduler is a

hierarchical weighted round-robin (HWRR) design, with 8 priority levels and drop-down reservations between

priority levels. Scheduling weights have a range of 1 to 255.

In addition to the per-Queue shaper/scheduler function, the Shaper/Scheduler blocks contain per-Priority and

Aggregate shapers. The per-Priority shaper allows shaping control of all FIFOs assigned to a given Priority level.

The Aggregate shaper allows shaping of the final, summed output of each Shaper/Scheduler block.

1.8 ARM9 Processor Subsystem

The ARM9 processor is responsible for running Teknovus OLT firmware. The ARM9 processor subsystem

consists of an embedded ARM946E processor running at 125MHz, plus:

• 8KB Data Cache

• 8KB Instruction Cache

• Memory Controller (interface to external 32-bit wide SDRAM and 16-bit wide FLASH)

• Watchdog timer

• Four general-purpose timers

• UART.

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