IMX7DCEC数据手册

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Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 6, 02/2019

NXP Semiconductors16

3.1 Special signal considerations

Table 3 lists special signal considerations for the i.MX 7Dual family of processors. The signal names are

listed in alphabetical order.

WDOG1

WDOG3

WDOG4

Watchdog Timer peripherals The Watch dog timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the Arm

core, and a second point evokes an external event on

the WDOG line.

WDOG2

(TrustZone)

Watchdog (TrustZone

technology)

Timer peripherals The TrustZone Watchdog (TZ WDOG) timer module

protects against TrustZone starvation by providing a

method of escaping Normal mode and forcing a switch

to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such

situation is undesirable as it can compromise the

system’s security. Once the TZ WDOG module is

activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the

timer times out. Upon a time-out, the TZ WDOG asserts

a TZ mapped interrupt that forces switching to the TZ

mode. If it is still not served, the TZ WDOG asserts a

security violation signal to the CSU. The TZ WDOG

module cannot be programmed or deactivated by a

normal mode SW.

Table 2. i.MX 7Dual modules list(continued)

Block Mnemonic Block Name Subsystem Brief Description

Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 6, 02/2019

NXP Semiconductors 17

The package contact assignments can be found in Section 6, “Package information and contact

assignments.” Signal descriptions are provided in the i.MX 7Dual Application Processor Reference

Manual (IMX7DRM).

Table 3. Special signal considerations

Signal Name Remarks

CCM_CLK1_P/

CCM_CLK1_N

CCM_CLK2

One general purpose differential high speed clock input/output and one single-ended clock input

are provided.

Either or both of them can be used:

• To feed an external reference clock to the PLLs and to the modules inside the SoC, for

example, as an alternate reference clock for PCIe, Video/Audio interfaces and so forth.

• To output the internal SoC clock to be used outside the SoC as either a reference clock or as

a functional clock for peripherals; for example, it can be used as an output of the PCIe master

clock (root complex use)

See the

i.MX 7Dual Application Processor Reference Manual

(IMX7DRM) for details on the

respective clock trees.

The CCM_CLK1_* inputs/outputs are an LVDS differential pair.

Alternatively, a single-ended signal may be used to drive CCM_CLK1_P input. In this case

corresponding CCM_CLK1_N input should be tied to the constant voltage level equal to 1/2 of the

input signal swing.

Termination should be provided in case of high frequency signals.

See the LVDS pad electrical specification for further details. CCM_CLK2 is a single-ended input

referenced to ground.

After initialization:

• The CCM_CLK1_* inputs/outputs can be disabled if not used. Any of the unused CCM_CLK1_*

pins may be left floating.

• The CCM_CLK2 input should be grounded if not used.

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. It

is recommended to use the configurable load capacitors provided in the IP instead of adding them

externally. To hit the exact oscillation frequency, the configurable capacitors need to be reduced

to account for board and chip parasitics.

The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit

parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M). This will

debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and

RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin

should be left floating or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level.

In the case when a high-accuracy realtime clock is not required, the system may use internal low

frequency oscillator. It is recommended to connect RTC_XTALI to ground and keep RTC_XTALO

floating. This will however result in increased power consumption, because the internal oscillator

uses higher power than the RTC oscillator. Thus for lowest power configuration it is recommended

to always install a crystal.

XTALI/XTALO A 24.0 MHz crystal should be connected between XTALI and XTALO.

Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 6, 02/2019

NXP Semiconductors18

DRAM_VREF When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use

a 1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with

a closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification)

is maintained when four DDR3 ICs plus the i.MX 7Dual are drawing current on the resistor divider.

It is recommended to use regulated power supply for “big” memory configurations (more than

eight devices)

ZQPAD DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

PCIE_VPH/PCIE_VPH_TX/

PCIE_VPH_RX

Short these pins to VDDA_PHY1P8 if using PCIe. User can tie these pins to ground if not using

PCIe.

PCIE_VP/PCIE_VP_TX/PC

IE_VP_RX

Short these pins to VDDD_1P0CAP if using PCIe. User can tie these pins to ground with a 10 KΩ

resistor if not using PCIe.

VDDA_MIPI_1P8 Short these pins to VDDA_PHY_1P8 if using MIPI. User can leave these pins floating or grounded

if not using MIPI.

VDD_MIPI_1P0 Short these pins to VDDD_1P0_CAP if using MIPI. User can leave these pins floating or grounded

if not using MIPI.

GPANAIO This signal is reserved for manufacturing use only. User must leave this connection floating.

JTAG_

nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an

external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the

i.MX 7Dual Application Processor Reference

Manual

(IMX7DRM). Both names refer to the same signal. JTAG_MOD must be externally

connected to GND for normal operation. Termination to GND through an external pull-down

resistor (such as 1 kΩ) is allowed. JTAG_MOD set to high configures the JTAG interface to a

mode compatible with the IEEE 1149.1 standard. JTAG_MOD set to low configures the JTAG

interface for common SW debug adding all the system TAPs to the chain.

NC Do not connect. These signals are reserved and should be floated by the user.

POR_B This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF In Normal mode, may be connected to ON/OFF button (De-bouncing provided at this input).

Internally this pad is pulled up. Short connection to GND in OFF mode causes internal power

management state machine to change state to ON. In ON mode short connection to GND

generates interrupt (intended to SW controllable power down). Long above ~5s connection to

GND causes “forced” OFF.

TEST_MODE TEST_MODE is for factory use. This signal is internally connected to an on-chip pull-down device.

The user must tie this signal to GND.

Table 3. Special signal considerations(continued)

Signal Name Remarks

Modules list

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 6, 02/2019

NXP Semiconductors 19

3.2 Recommended connections for unused analog interfaces

Table 5 shows the recommended connections for unused analog interfaces.

PCIE_REXT The impedance calibration process requires connection of reference resistor 4.7 KΩ 1% precision

resistor on PCIE_REXT pad to ground.

USB_OTG1_REXT/USB_O

TG2_REXT

The bias generation and impedance calibration process for the USB OTG PHYs requires

connection of 200 Ω (1% precision) reference resistors on each of the USB_OTG1_REXT and

USB_OTG2_REXT pads to ground.

USB_OTG1_CHD_B An external pullup resistor with value in range from 10 kΩ to 100 kΩ should be connected

between open-drain output USB_OTG1_CHD_B and supply VDD_USB_OTG1_3P3_IN for 3.3 V

signaling. Optionally, a similarly valued pullup resistor could be connected instead between

USB_OTG1_CHD_B and an unrelated supply up to 1.8 V, but in that case the output is only valid

when both that supply and VDD_USB_OTG1_3P3_IN are powered.

TEMPSENSOR_REXT External 100 KΩ (1% precision) resistor connection pin

Table 4. JTAG controller interface summary

JTAG I/O Type On-chip Termination

JTAG_TCK Input 47 kΩ

pull-up

JTAG_TMS Input 47 kΩ

pull-up

JTAG_TDI Input 47 kΩ

pull-up

JTAG_TDO 3-state output 100 kΩ pull-up

JTAG_TRSTB Input 47 kΩ

pull-up

JTAG_MOD Input 100 kΩ

pull-up

Table 5. Recommended connections for unused analog interfaces

Module Package Net Name

Recommendation

if Unused

ADC VDDA_ADC2_1P8, VDDA_ADC2_1P8, VDDA_ADC1_1P8,

VDDA_ADC1_1P8

1.8 V

ADC2_IN3, ADC2_IN2, ADC2_IN1, ADC2_IN0, ADC1_IN0,

ADC1_IN1, ADC1_IN2, ADC1_IN3

Tie to ground

LDO VDD_1P2_CAP Floating if USB_HSIC is not used

MIPI VDD_MIPI_1P0, VDDA_MIPI_1P8 Floating or tie to ground

MIPI_DSI_D0_N, MIPI_DSI_D0_P, MIPI_VREG_0P4V,

MIPI_DSI_CLK_N, MIPI_DSI_CLK_P, MIPI_DSI_D1_N,

MIPI_DSI_D1_P, MIPI_CSI_D0_N, MIPI_CSI_D0_P,

MIPI_CSI_CLK_N, MIPI_CSI_CLK_P, MIPI_CSI_D1_N,

MIPI_CSI_D1_P

No connect

Table 3. Special signal considerations(continued)

Signal Name Remarks

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