FPGA设计经验分享：100个实用技巧

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"《100_Power_Tips_for_FPGA_Designers_Stavinov_Evgeni》是由Evgeni Stavinov撰写的一本关于FPGA设计的实用技巧书籍，作者在FPGA领域积累了丰富的经验和知识，并希望通过本书与更广泛的读者分享。书中涵盖了FPGA设计的各种技术和策略，旨在帮助工程师提升设计效率和优化设计方案。" 本书写作过程中，Evgeni Stavinov得到了来自SerialTek公司的同事、前Xilinx公司的同事、技术博主以及许多其他人的宝贵建议、技术审核和编辑支持。书中的内容包括设计技巧、文本、图形、内容的选择和排列，以及所有其他信息，都体现了作者的专业技能和独特见解。标签"**fpga**"和"**xilinx**"表明这本书主要关注的是现场可编程门阵列（FPGA）的设计，特别是与Xilinx公司相关的产品和技术。书中可能涉及Xilinx的Spartan、Virtex系列FPGA，以及Xilinx ISE开发工具和Zynq系统级芯片（SoC）等。部分内容提到，书中包含的内容受到版权保护，未经作者Evgeni Stavinov的书面许可，不得以任何形式复制或传播。同时，书中提及了多家公司在FPGA设计工具领域的商标，如Cadence的Incisive Palladium和NCSim，Aldec的Riviera-PRO和Active-HDL，Synopsys的Synplify Pro，以及Altera的Stratix和Cyclone等，这些都是行业内的知名产品。此外，书中声明了责任限制和免责声明，指出在法律允许的最大范围内，作者不承担任何间接、特殊或后果性的损失，也不提供任何明示或暗示的保修，这在出版物中是常见的法律保护措施。《100 Power Tips for FPGA Designers》是一本面向FPGA设计师的实用指南，涵盖了设计过程中的各种技巧和最佳实践，适合想要提高FPGA设计能力的工程师参考学习。书中融入了作者的个人经验和业界专家的智慧，对于理解FPGA设计流程、优化设计方法和掌握相关工具的使用具有很高的价值。

Figure 2: Xilinx Virtex-6 FPGA Slice structure

The connectivity between LUTs, registers, multiplexers, and a carry chain can be configured to form

different logic circuits.

There are two different Slice types: SLICEM and SLICEL. A SLICEM has a multi-purpose LUT, which

can also be configured as a Shift Register LUT (SRL), or a 64- or 32-bit read-only or random access

memory.

Each Slice register can be configured as a latch.

Clocking resources

Each Virtex-6 FPGA provides several highly configurable mixed-mode clock managers (MMCMs),

which are used for frequency synthesis and phase shifting.

Clocks to different synchronous elements across FPGA are distributed using dedicated low-skew and

low-delay clock routing resources. Clock lines can be driven by global clock buffers, which allow

glitchless clock multiplexing and the clock enable.

More detailed discussion of Xilinx FPGA clocking resources is provided in Tip #20.

Embedded memory

Xilinx FPGAs have two types of embedded memories: a dedicated Block RAM (BRAM) primitive, and a

LUT configured as Distributed RAM

Virtex-6 BRAM can store 36K bits, and can be configured as a single- or dual-ported RAM. Other

configuration options include data width of up to 36-bit, memory depth up to 32K entries, and error

detection and correction.

Tip #34 describes different use cases of FPGA-embedded memory.

DSP

Virtex-6 FPGAs provide dedicated Digital Signal Processing (DSP) primitives to implement various

functions used in DSP applications, such as multipliers, accumulators, and signed arithmetic operations.

The main advantage of using DSP primitives instead of general-purpose LUTs and registers is high

performance.

Tip #28 describes different use cases of DSP primitive.

Input/Output

Input/Output (IO) block enables different IO pin configurations: IO standards, single-ended or differential,

slew rate and the output strength, pull-up or pull-down resistor, digitally controlled impedance (DCI). An

IO in Virtex-6 can be delayed by up to 32 increments of 78 ps each by using an IODELAY primitive.

Serializer/Deserializer

Most of Virtex-6 FPGAs include dedicated transceiver blocks that implement Serializer/Deserializer

(SerDes) circuits. Transceivers can operate at a data rate between 155 Mb/s and 11.18 Gb/s, depending

on the configuration.

Routing resources

FPGA routing resources provide programmable connectivity between logic blocks, IOs, embedded

memory, DSP, and other modules. Routing resources are arranged in a horizontal and vertical grid. A

special interconnect module serves as a configurable switch box to connect logic blocks, IOs, DSP, and

other module to horizontal and vertical routing. Unfortunately, Xilinx doesn’t provide much

documentation on performance characteristics, implementation details, and quantity of the routing

resources. Some routing performance characteristics can be obtained by analyzing timing reports. And the

FPGA Editor tool can be used to glean information about the routing quantity and structure.

FPGA configuration

The majority of modern FPGAs are SRAM-based, including Xilinx Spartan and Virtex families. On each

FPGA power-up, or during a subsequent FPGA reconfiguration, a bitstream is read from the external non-

volatile memory (NVM), processed by the configuration controller, and loaded to the internal

configuration SRAM. Tips #35-37 describe the process of FPGA configuration and bitstream structure in

more detail.

The following table summarizes this Tip by showing key features of the smallest, mid-range, and largest

Xilinx Virtex-6 FPGA.

Table 1: Xilinx Virtex-6 FPGA key features

XC6

VLX75T

XC6

VLX240T

XC6

VLX760

large multi-FPGA product, such as an ASIC prototyping platform, military communication system, or

high-end switch, the document is hundreds of pages long and written by several people.

Architecture specification

Architecture specification is based upon project specification. It is typically written by the most

experienced engineer in a team, the system architect, who has broad experience in hardware, logic, and

software design, is well-versed in writing specifications, and has good interpersonal skills. This engineer

interacts closely with the sales and marketing team to clarify and adjust the requirements if needed.

Architecture specification addresses issues such as the technical feasibility of the project, top-level block

diagram (which describes the partition between different components), main interfaces, and possible

implementation options.

It is important to perform feasibility analysis at this stage to find that the project requirements are realistic

and attainable and can meet performance, cost, size, and other goals.

An example of unrealistic requirement is a required processing speed of a deep-packet inspection engine

that cannot be done in real time using the latest FPGAs. One solution is to plan using the next FPGA

family that will be ready for production by the time the project enters the debug phase. Engineering

samples might be used in the interim.

Software, hardware, and logic top-level block diagrams should include main interfaces. The interfaces

have to be accurate, unambiguous, and interpreted the same way by all team members. The specification

also includes overall partitioning into multiple FPGAs and interfaces between them.

Architecture specification is a living document. It has to be maintained and kept up-to-date. Engineering

team members refer to the document to write more detailed block-level documents and to do design work.

Sales and marketing teams use it to establish bill of material (BOM) and final product cost.

FPGA selection

FPGA selection process involves selecting FPGA vendor, family, capacity, and speed grade. It is not

uncommon that a multi-FPGA project contains FPGAs from different vendors and families. It is typically

not an issue to interface between heterogeneous FPGAs as soon as they meet project requirements.

Selecting FPGAs from different vendors complicates some of the project management tasks, such as

having multiple tool flows and purchasing from different distributors. One of the reasons to select FPGAs

from different vendors is that each vendor offers unique features. Examples are integrated memory

controllers, SerDes that can operate at certain speed, logic capacity, or number of user IOs.

FPGA capacity estimate

FPGA capacity estimate, general guidelines and criteria for ASIC designs are discussed in more detail in

Tip #38.

The most reliable way to do size estimate is to build a final RTL implementation. In some cases this is

possible, such as in projects that require migration of an existing RTL base to the latest FPGA with

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FPGA设计经验分享：100个实用技巧

100 Power Tips for FPGA Designers

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