TI-TLV5535-Q1：汽车级高速8位ADC技术规格

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"TI-TLV5535-Q1.pdf" TI-TLV5535-Q1是一款专为汽车应用设计的高性能模拟数字转换器（ADC），满足AEC-Q100标准，具备8位分辨率和35兆样本每秒（MSPS）的采样率。这款ADC的主要特点包括低功耗、宽模拟输入带宽和单3.3伏电源操作。 1. 8位分辨率：TLV5535提供8位的数字输出，能够将模拟信号转换成8位二进制编码的数字字，确保在高采样率下仍能保持一定的精度。 2. 35MSPS采样率：高速采样能力使得该ADC适用于需要快速处理模拟信号的系统，如数字通信中的中频采样或高速数字信号处理前端。 3. 低功耗：典型工作状态下，其功耗仅为90毫瓦，这使得它适合在对电源效率有严格要求的车载应用中使用。 4. 宽模拟输入带宽：600MHz的典型输入带宽允许该器件处理高频模拟信号，使其在视频处理和DVD读取通道数字化等应用中表现出色。 5. 3.3V单电源操作：只需要3.3V的电源电压，简化了电源管理，并与常见的3.3V TTL/CMOS兼容的数字输入和输出接口。 6. 内部基准电压：包含内部底部和顶部参考电压，提供稳定且准确的转换基准。 7. 可调整的参考输入范围：允许用户根据应用需求定制参考电压，增加了设计的灵活性。 8. 电源down模式：支持电源down（待机）模式，进一步降低了功耗，有助于节省能源。 9. 独立的内部电压参考电源down：可以单独控制内部电压参考的电源down状态，增强了系统级的电源管理能力。 10. 三态输出：采用三态输出设计，能够在不需要输出时使输出进入高阻态，提高系统设计的灵活性。 11. 28引脚薄型缩小型小外形封装（TSSOP）：紧凑的封装设计适应了空间有限的电路板布局。 12. 应用领域： - 数字通信：用于中频采样，提高数据传输效率。 - 高速数字信号处理前端：与TMS320C6000等DSP芯片配合，处理高速信号。 - 视频处理：在扫描速率和格式转换中发挥作用，实现高质量的视频输出。 - DVD读取通道数字化：用于将模拟音频和视频信号转换为数字格式，提升读取质量。 TI-TLV5535-Q1是一款适用于汽车电子系统的高性能、低功耗8位ADC，它的设计考虑了汽车环境的严苛要求，同时提供了高速转换和广泛的灵活性，适用于各种实时信号处理应用场景。

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SGLS230A − JANUARY 2004 − REVISED JUNE 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

reference input (AV

= DV

= DRV

= 3.6 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ref

Reference input resistance 400 Ω

ref

Reference input current 2.5 mA

reference outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(REFTO)

Reference top offset voltage

Absolute min/max values valid

2.07 2 + [(AV

− 3) ÷ 2] 2.21 V

(REFBO)

Reference bottom offset voltage

Absolute min/max values valid

and tested for AV

= 3.3 V

1.09 1 + [(AV

− 3) ÷ 2] 1.21 V

dynamic performance

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 1 MHz 6.6 7.4

Effective number of bits (ENOB)

= 4.2 MHz 6.6 7.4

Bits

Effective number of bits (ENOB)

= 15 MHz 7

Bits

= 1 MHz 41.5 46

Signal-to-noise ratio + distortion (SNRD)

= 4.2 MHz 41.5 46

Signal-to-noise ratio + distortion (SNRD)

= 15 MHz 43

= 1 MHz −46 −55

Total harmonic distortion (THD)

= 4.2 MHz −45.5 −54

Total harmonic distortion (THD)

= 15 MHz −50

= 1 MHz 48 58

Spurious free dynamic range (SFDR)

= 4.2 MHz 48 58

Spurious free dynamic range (SFDR)

= 15 MHz 52

Analog input full-power bandwidth, BW See Note 4 600 MHz

Differential phase, DP

CLK

= 35 MHz, f

= 4.2 MHz,

0.6

Differential phase, DP

CLK

= 35 MHz, f

= 4.2 MHz,

0.6

Differential gain, DG

CLK

= 35 MHz, f

= 4.2 MHz,

20 IRE amplitude vs full-scale of 140 IRE

0.2%

Differential gain, DG

20 IRE amplitude vs full-scale of 140 IRE

0.2%

†

Based on analog input voltage of −1-dB FS referenced to a 1.3 V

full-scale input range and using the external voltage references at

CLK

= 35 MSPS with AV

= DV

= 3.3 V and DRV

= 3 V at 25°C.

NOTE 4: The analog input bandwidth is defined as the maximum frequency of a −1-dB FS input sine that can be applied to the device for which

an extra 3-dB attenuation is observed in the reconstructed output signal.



     

SGLS230A − JANUARY 2004 − REVISED JUNE 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLK

Maximum conversion rate 35 MHz

CLK

Minimum conversion rate 10 kHz

d(o)

Output delay time (see Figure 1) C

= 10 pF, See Notes 5 and 6 9 ns

h(o)

Output hold time C

= 2 pF, See Note 5 2 ns

d(pipe)

Pipeline delay time (latency) See Note 6 4.5 4.5 4.5

CLK

cycles

d(a)

Aperture delay time 3 ns

j(a)

Aperture jitter

See Note 5

1.5 ps, rms

dis

Disable time, OE rising to Hi-Z

See Note 5

5 8 ns

Enable time, OE falling to valid data 5 8 ns

NOTES: 5. Output timing t

d(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital

output load is not higher than 10 pF.

Output hold time t

h(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

digital output is load is not less than 2 pF.

Aperture delay t

d(A)

is measured from the 1.5 V level of the CLK input to the actual sampling instant.

The OE signal is asynchronous.

OE timing t

dis

is measured from the V

IH(MIN)

level of OE to the high-impedance state of the output data. The digital output load is

not higher than 10 pF.

OE timing t

is measured from the V

IL(MAX)

level of OE to the instant when the output data reaches V

OH(min)

or V

OL(max)

output

levels. The digital output load is not higher than 10 pF.

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made

available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to

know when data is stable on the output pins, the output delay time t

d(o)

(i.e., the delay time through the digital output buffers) needs

to be added to the pipeline latency. Note that since the max t

d(o)

is more than 1/2 clock period at 35 MHz, data cannot be reliably

clocked in on a rising edge of CLK at this speed. The falling edge should be used.

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