STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3编程手册：应用与系统开发指南

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本篇《ContexM3编程手册》专为应用和系统级软件开发者设计，详细介绍了STM32F10xxx/20xxx/21xxx/L1xxxx系列Cortex-M3处理器的编程模型、指令集以及核心外围设备。该手册发布于2011年3月，文档编号为DocID15491Rev4。首先，手册强调了Cortex-M3处理器在高性能微控制器市场中的优势。它结合了卓越的处理性能与快速中断处理能力，这使得开发人员能够实现高效的应用程序运行和响应时间。同时，它提供了丰富的系统调试功能，包括广泛的断点设置和跟踪能力，便于深入分析和优化代码。处理器的核心特点还包括高效的处理器内核、系统和内存管理，确保资源的有效利用。此外，低功耗是其另一大亮点，集成的睡眠模式有助于在不影响功能的前提下显著降低能耗，对于能源效率要求高的应用非常关键。安全平台也是STM32F10xxx/20xxx/21xxx/L1xxxx系列的一大卖点，为用户提供了可靠的数据保护和系统安全措施。手册的第一部分概述了文档本身，包括排版约定、缩略语表，以及对STM32 Cortex-M3处理器和核心外围设备的详细介绍。系统级接口部分介绍了处理器与外设之间的交互方式，而内核的详细规格和配置选项则在后续章节中展开，以便开发人员根据项目需求进行适配和定制。为了充分利用这些特性，读者可以参考手册中的示例代码、API文档和架构图，学习如何在实际项目中正确配置和驱动处理器的各个模块。同时，手册还包含了错误处理、中断管理、存储器管理以及电源管理和唤醒机制等相关知识，帮助开发者优化代码并提高系统整体性能。《ContexM3编程手册》为开发STM32F10xxx/20xxx/21xxx/L1xxxx系列处理器的应用和系统级软件提供了一个全面且详尽的指南，是开发人员不可或缺的参考资料。通过深入理解和掌握其中的知识，开发者将能更好地利用Cortex-M3处理器的强大功能，提升产品的性能和竞争力。

The Cortex-M3 processor PM0056

16/155 Doc ID 15491 Rev 4

General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register

indicates the stack pointer to use:

● 0 = Main Stack Pointer (MSP). This is the reset value.

● 1 = Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

Link register

The Link Register (LR) is register R14. It stores the return information for subroutines,

function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.

Program counter

The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is

always 0 because instruction fetches must be halfword aligned. On reset, the processor

loads the PC with the value of the reset vector, which is at address 0x00000004.

LR read-write Either 0xFFFFFFFF Link register on page 16

PC read-write Either See description Program counter on page 16

PSR read-write Privileged 0x01000000 Program status register on page 17

ASPR read-write Either 0x00000000

Application program status register on

page 18

IPSR read-only Privileged 0x00000000

Interrupt program status register on

page 19

EPSR read-only Privileged 0x01000000

Execution program status register on

page 20

PRIMASK read-write Privileged 0x00000000 Priority mask register on page 21

FAULTMASK read-write Privileged 0x00000000 Fault mask register on page 21

BASEPRI read-write Privileged 0x00000000 Base priority mask register on page 22

CONTROL read-write Privileged 0x00000000 CONTROL register on page 22

1. Describes access type during program execution in thread mode and Handler mode. Debug access can

differ.

2. An entry of Either means privileged and unprivileged software can access the register.

Table 2. Core register set summary (continued)

Name Type

(1)

Required

privilege

(2)

Reset

value

Description

The Cortex-M3 processor PM0056

20/155 Doc ID 15491 Rev 4

Execution program status register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

● If-Then (IT) instruction

● Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store

multiple instruction.

See the register summary in Table 2 on page 15 for the EPSR attributes. The bit

assignments are:

Attempts to read the EPSR directly through application software using the MSR instruction

always return zero. Attempts to write the EPSR using the MSR instruction in application

software are ignored. Fault handlers can examine EPSR value in the stacked PSR to

indicate the operation that is at fault. See Section 2.3.7: Exception entry and return on

page 38

Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM or STM instruction, the processor:

● Stops the load multiple or store multiple instruction operation temporarily

● Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

● Returns to the register pointed to by bits[15:12]

● Resumes execution of the multiple load or store instruction.

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

If-Then block

The If-Then block contains up to four instructions following a 16-bit IT instruction. Each

instruction in the block is conditional. The conditions for the instructions are either all the

same, or some can be the inverse of others. See IT on page 95 for more information.

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks.

To access the exception mask registers use the MSR and MRS instructions, or the CPS

instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 101, MSR

on page 102, and CPS on page 99 for more information.

Table 6. EPSR bit definitions

Bits Description

Bits 31:27 Reserved.

Bits 26:25, 15:10 ICI: Interruptible-continuable instruction bits

See Interruptible-continuable instructions on page 20.

Bits 26:25, 15:10 IT: Indicates the execution state bits of the IT instruction, see

IT on page 95.

Bit 24 Always set to 1.

Bits 23:16 Reserved.

Bits 9:0] Reserved.

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