SLUS165C – MARCH 1999 - REVISED JANUARY 2002
3
www.ti.com
electrical characteristics, these specifications apply for T
A
= –55°C to 125°C for UC1907, –40°C to
85°C for UC2907, and 0°C to 70°C for UC3907, V
IN
= 15 V, T
A
= T
J
(unless otherwise stated )
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Voltage Amp Section
Inp t oltage
COMP = 1 V, T
A
= 25°C 1.975 2.000 2.025 V
Input voltage
COMP = 1 V, over temp 1.960 2.000 2.040 V
Line regulation V
IN
= 4.5 V to 35 V 15 mV
Load regulation I
L
reference = 0.0 mA to –10 mA 10 mV
Long term stability T
A
= 125°C, 1000hrs See Note 2 5 25 mV
Total output variation Line, load, temp 1.960 2.040
Input adjust range ADJ OUT from max high to max low 85 100 115 mV
Input bias current –1 µA
Open loop gain COMP = 0.75 V to 1.5 V 65 dB
Unity gain bandwidth T
A
= 25°C See Note 2 700 kHz
Output sink current (+) SENSE = 2.2 V, COMP = 1 V 6 15 mA
Output source current (+) SENSE = 1.8 V, COMP = 1 V 400 600 µA
V
OUT
high (+) SENSE = 1.8 V, I
L
= –400 µΑ 1.85 2 V
V
OUT
low (+) SENSE = 2.2 V, I
L
= 1 mA 0.15 0.40 V
Reference Section
O tp t oltage
T
A
= 25°C 1.970 2.000 2.030 V
Output voltage
Over operating temp 1.955 2.000 2.045 V
Short circuit current VREF = 0.0 V –15 –30 –60 mA
Ground Amp Section
Output voltage 200 250 300 mV
Common mode variation (–) SENSE from 0.0 V to 2 V 5 mV
Load reg lation
I
L
= 0.0 mA to 20 mA, T
A
= 25°C 10 mV
Load regulation
I
L
= 0.0 mA to 20 mA, over temp 15 mV
Adjust Amp Section
Input offset voltage ADJ OUT = 1.5 V, V
CM
= 0.0 V 40 50 60 mV
Input bias current –2 µA
Open loop gain 1.5 V ≤ ADJ OUT ≤ 2.25 V 65 dB
Unity gain bandwidth T
A
= 25°C, C
OUT
=1 µF See Note 2 500 Hz
Transconductance I
OUT
= –10 µA to 10 µA, V
OUT
= 1.5 V 1.7 3 4.5 ms
Output sink current V
ID
= 0.0 V, ADJ OUT = 1.5 V 55 135 225 µA
Output source current V
ID
= 250 mV, ADJ OUT = 1.5 V 110 200 350 µA
V
OUT
high V
ID
= 250 mV, I
OUT
= – 50 mA 2.20 2.70 2.90 V
V
OUT
low V
ID
= 0.0 V, I
OUT
= 50 mA 0.75 1.15 V
Common mode rejection ratio V
CM
= 0.0 to 10 V 70 dB
Output gain to V/A
V
OUT
ADJ OUT = 1.5 V to 2 V,
∆(+) SENSE/ ∆ADJ OUT
50 57 64 mV/V
NOTE 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the specified terminal.
NOTE 2: Ensured by design. Not production tested.
剩余11页未读，继续阅读
不觉明了
- 粉丝: 3443
- 资源: 5759
我的内容管理
展开
最新资源
- WebLogic集群配置与管理实战指南
- AIX5.3上安装Weblogic 9.2详细步骤
- 面向对象编程模拟试题详解与解析
- Flex+FMS2.0中文教程：开发流媒体应用的实践指南
- PID调节深入解析：从入门到精通
- 数字水印技术：保护版权的新防线
- 8位数码管显示24小时制数字电子钟程序设计
- Mhdd免费版详细使用教程：硬盘检测与坏道屏蔽
- 操作系统期末复习指南：进程、线程与系统调用详解
- Cognos8性能优化指南：软件参数与报表设计调优
- Cognos8开发入门：从Transformer到ReportStudio
- Cisco 6509交换机配置全面指南
- C#入门：XML基础教程与实例解析
- Matlab振动分析详解：从单自由度到6自由度模型
- Eclipse JDT中的ASTParser详解与核心类介绍
- Java程序员必备资源网站大全
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
