STM32G071C8 Cortex-M0+ MCU 数据手册：高性能、低功耗特性

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"STM32G071C8是一款基于Arm Cortex-M0+内核的32位微控制器，由意法半导体（STMicroelectronics）制造，适用于各种嵌入式应用。该芯片具备高性能、低功耗的特点，并提供丰富的外设接口。" STM32G071C8的主要特性包括： 1. **核心处理器**: 配备了Arm Cortex-M0+ CPU，工作频率最高可达64MHz，提供了高效能的计算能力。 2. **温度范围**: 可在-40°C到85°C，甚至105°C或125°C的宽温范围内正常工作，适应不同环境需求。 3. **内存配置**: 提供最大128KB的闪存（Flash Memory），支持保护和安全区域功能；集成36KB的SRAM，其中32KB带有硬件奇偶校验检查，确保数据完整性。 4. **CRC计算单元**: 支持循环冗余校验（CRC）计算，用于检测和防止数据传输错误。 5. **复位与电源管理**: 包括电压范围1.7V至3.6V，上电/掉电复位（POR/PDR）、可编程欠压复位（BOR）、可编程电压检测器（PVD），以及多种低功耗模式，如睡眠、停止、待机和关断。还支持VBAT供电，为RTC（实时时钟）和备份寄存器提供电源。 6. **时钟管理**: 内置4到48MHz的晶体振荡器，32kHz晶体振荡器带校准功能，16MHz内部RC振荡器带PLL选项（精度±1%），以及32kHz内部RC振荡器（精度±5%）。 7. **输入/输出（I/O）**: 最多提供60个快速I/O，所有I/O都可以映射到外部中断向量，且有多个5V耐受的I/O，增强了接口兼容性。 8. **DMA控制器**: 7通道DMA控制器，具有灵活的映射功能，提高了数据传输效率。 9. **模拟功能**: 包含12位ADC（模数转换器），转换时间仅为0.4µs，最多可连接16个外部通道，适用于各种传感器信号采集。 10. **其他外设**: 除上述特性外，STM32G071C8还可能包含定时器、DAC（数模转换器）、通信接口等，使得它适合于众多应用领域，如物联网设备、工业控制、消费电子和嵌入式系统等。 STM32G071C8的数据手册提供了完整的电气特性和应用指南，是开发者设计基于此芯片系统的必备参考资料。通过深入理解和利用这些特性，开发者可以构建出高效、可靠且低功耗的嵌入式解决方案。

Functional overview STM32G071x8/xB

16/133 DS12232 Rev 3

3.4 Embedded SRAM

STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity

check allows memory data errors to be detected, which contributes to increasing functional

safety of applications.

When the parity protection is not required because the application is not safety-critical, the

parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector

option bit. The boot loader is located in System memory. It manages the Flash memory

reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I

C-

bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or

PB12/PB13/PB14/PB15.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link

time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (V

Several different power supplies are provided to specific peripherals:

• V

= 1.7 (1.6) to 3.6 V

is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold

POR

(max). Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold V

PDR

(min).

DS12232 Rev 3 19/133

STM32G071x8/xB Functional overview

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the V

CORE

domain. The PLL, as well as the

Functional overview STM32G071x8/xB

20/133 DS12232 Rev 3

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (V

BAT

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

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