VHDL 2005电路设计入门指南

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"Circuit Design with VHDL 2005 MIT Press" 是一本关于使用VHDL进行电路设计的专业书籍，适合初学者和作为课程参考。作者是Volnei A. Pedroni，由MIT Press出版。这本书包含了丰富的实例，有助于读者理解和掌握VHDL在电子电路设计和系统设计中的应用。 VHDL（Very High-Speed Integrated Circuit Hardware Description Language）是一种硬件描述语言，用于描述数字系统的结构、行为和功能。在电子工程领域，VHDL被广泛用于设计和验证数字集成电路以及FPGA（Field-Programmable Gate Array）和ASIC（Application-Specific Integrated Circuit）等可编程逻辑器件。这本书的核心就是教授读者如何使用VHDL进行有效的电路设计。书中首先介绍了VHDL的基本概念，包括其语法结构和使用方式，让读者了解VHDL如何描述不同的电路组件，如门电路、触发器和移位寄存器等。通过学习VHDL，读者可以将抽象的逻辑设计转化为具体的硬件实现。此外，书中还可能涵盖了VHDL的库、实体、架构、过程、类型和操作符等关键元素。电路设计章节可能会逐步引导读者完成从简单逻辑门到复杂数字系统的建模。这些设计通常会涉及组合逻辑电路和时序逻辑电路的设计，包括计数器、加法器、存储器等。作者Volnei A. Pedroni通过实例展示了如何利用VHDL进行设计仿真和验证，确保设计的正确性。除了基本的电路设计，书中的内容可能还会扩展到系统层面，讨论如何使用VHDL进行模块化设计，以及如何将不同模块集成到一个完整的系统中。这可能包括接口设计、时钟管理、错误检测与校正等高级主题。此外，书中的参考文献和索引提供了进一步学习和深入研究的资源。 "Circuit Design with VHDL 2005 MIT Press"是一本实用的教材，它不仅教授VHDL语言，还提供了丰富的实践案例，帮助读者提升电子电路设计和系统设计的能力。对于希望进入或深化数字系统设计领域的专业人士来说，这本书无疑是一个有价值的资源。

1Introduction

1.1 About VHDL

VHDL is a hardware description language.It describes the behavior of an electronic

circuit or system, from which the physical circuit or system can then be attained

(implemented).

VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an

abbreviation for Very High Speed Integrated Circuits, an initiative funded by the

United States Department of Defense in the 1980s that led to the creation of VHDL.

Its ﬁrst version was VHDL 87, later upgraded to the so-called VHDL 93. VHDL

was the original and ﬁrst hardware description language to be standardized by the

Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard.

An additional stand ard, the IEEE 1164, was later added to introduce a multi-valued

logic system.

VHDL is intended for circuit synthesis as well as circuit simulation. However,

though VHDL is fully simulatable, not all constructs are synthesizable. We will give

emphasis to those that are.

A fundamental motivation to use VHDL (or its competitor, Verilog) is that

VHDL is a standard, technology/vendor independent language, and is therefore

portable and reusable. The two main immediate applications of VHDL are in the

ﬁeld of Programmable Logic Devices (including CPLDs—Complex Programmable

Logic Devices and FPGAs—Field Programmable Gate Arrays) and in the ﬁeld of

ASICs (Application Speciﬁc Integrated Circuits). Once the VHDL code has been

written, it can be used either to implement the circuit in a programmable device

(from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication

of an ASIC chip. Currently, many complex commercial chips (microcontrollers, for

example) are designed using such an approach.

A ﬁnal note regarding VHDL is that, contrary to regular computer programs

which are sequential, its statements are inherently concurrent (parallel). For that

reason, VH DL is usually referred to as a code rather than a program. In VHDL,

only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are

executed sequentially.

1.2 Design Flow

As mentioned above, one of the major utilities of VHDL is that it allows the syn-

thesis of a circuit or system in a programmable device (PLD or FPGA) or in an

ASIC. The steps followed during such a project are summarized in ﬁgure 1.1. We

start the design by writing the VHDL code, which is saved in a ﬁle with the extension

TLFeBOOK

sizers, for example), bes ides being o¤ered as part of the design suites, can also be

provided by specialized ED A companies (Mentor Graphics, Synopsis, Synplicity,

etc.). Examples of the latter group are Leonardo Spectrum (a synthesizer from

Mentor Graphics), Synplify (a synthesizer from Synplicity), and ModelSim (a simu-

lator from Model Technology, a Mentor Graphics company).

The designs presented in the book were synthesized onto CPLD/FPGA devices

(appendix A) either from Altera or Xilinx. The tools used were either ISE combined

with ModelSim (for Xilinx chips—appendix B), MaxPlus II combined with Ad-

vanced Synthesis Software (for Altera CPLDs—appendix C), or Quartus II (also

for Altera devices—appendix D). Leonardo Spectrum was also used occasionally.

Although di¤erent EDA tools were used to implement and test the examples

presented in the book (see list of tools above), we decided to standardize the visual

presentation of all simulation graphs. Due to its clean appearance, the waveform

editor of MaxPlus II (appendix C) was employed. However, newer simulators, like

ISE þ ModelSim (appendix B) and Quartus II (appendix D), o¤er a much broader

set of features, which allow, for example, a more reﬁned timing analysis. For that

reason, those tools were adopted when examining the ﬁne details of each des ign.

1.4 Translation of VHDL Code into a Circuit

A full-adder unit is depicted in ﬁgure 1.2. In it, a and b represent the input bits to be

added, cin is the carry-in bit, s is the sum bi t, and cout the carry-out bit. As shown in

the truth table, s must be high whenever the number of inputs that are high is odd,

while cout must be high when two or more inputs are high.

A VHDL code for the full adder of ﬁgure 1.2 is shown in ﬁgure 1.3. As can be

seen, it consists of an ENTITY, which is a description of the pins (PORTS) of the

Full

Adder

cin

cout

a b cin s cout

0 0 0

0 1 0

1 0 0

1 1 0

0 0

1 0

0 1

0 0 1

0 1 1

1 0 1

1 1 1

1 0

0 1

Figure 1.2

Full-adder diagram and truth table.

Introduction 5

TLFeBOOK

circuit, and of an ARCHITECTURE , which describes how the circuit should func-

tion. We see in the latter that the sum bit is computed as s ¼ a a b a cin, while cout

is obtained from cout ¼ a.b þ a.cin þ b.cin.

From the VHDL code shown on the left-hand side of ﬁgure 1.3, a physical circuit

is inferred, as indicated on the right-hand side of the ﬁgure. However, there are sev-

eral ways of implementing the equations described in the ARCHITECTURE of

ﬁgure 1.3, so the actual circuit will depend on the compiler/optimizer being used and,

more importantly, on the target technology. A few examples are presented in ﬁgure

1.4. For instance, if our target is a programmable logic dev ice (PLD or FPGA—

appendix A), then two possible results (among many others) for cout are illustrated

in ﬁgures 1.4(b)–(c) (in both, of course, cout ¼ a.b þ a.cin þ b.cin). On the other

hand, if our target technology is an ASIC, then a possible CMOS implementation, at

the transistor level, is that of ﬁgure 1.4(d) (which makes use of MOS transistors and

clocked domino logic). Moreover, the synthesis tool can be set to optimize the layout

for area or for speed, which obviously also a¤ects the ﬁnal circuitry.

Whatever the ﬁnal circuit inferred from the code is, its operation should always be

veriﬁed still at the design level (after synthesis), as indicated in ﬁgure 1.1. Of course,

it must also be tested at the physical level, but then changes in the design might be

too costly.

When testing, waveforms similar to those depicted in ﬁgure 1.5 will be displayed

by the simulator. Indeed, ﬁgure 1.5 contains th e simulation results from the circuit

synthesized with the VHDL code of ﬁgure 1.3, which implements the full-adder unit

of ﬁgure 1.2. As can be seen, the input pins (characterized by an inward arrow with

an I marked inside) and the output pins (characterized by an outward arrow with an

O marked inside) are those listed in the ENTITY of ﬁgure 1.3. We can freely estab-

ENTITY full_adder IS

PORT (a, b, cin: IN BIT;

s, cout: OUT BIT);

END full_adder;

--------------------------------------

ARCHITECTURE dataflow OF full_adder IS

BEGIN

s <= a XOR b XOR cin;

cout <= (a AND b) OR (a AND cin) OR

(b AND cin);

END dataflow;

Circuit

Figure 1.3

Example of VHDL code for the full-adder unit of ﬁgure 1.2.

6 Chapter 1

TLFeBOOK

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VHDL 2005电路设计入门指南

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MIT.Press.Circuit.Design.With.VHDL.

MIT.Press.Circuit.Design.With.VHDL.pdf（破解版，可编辑打印）

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