KeyStone多核架构：TI TCI6636K2H DSP+ARM SoC

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"TI的KeyStone架构是一种高性能的多核架构，用于集成RISC和DSP核心，以及应用特定协处理器和I/O。该架构通过四个主要硬件元素实现非阻塞访问所有处理核心、外围设备、协处理器和I/O：多核导航器、TeraNet、多核共享内存控制器和HyperLink。TCI6636K2H是基于KeyStone II的SoC，包含了8个C66x DSP核心子系统和4个ARM Cortex-A15 CPU，适用于LTE调制解调器等应用。" TI的KeyStone架构是集成电路设计中的一个创新，它提供了首个能够确保内部带宽足够，使得所有处理核心、外设、协处理器和I/O非阻塞访问的平台。这个架构的核心组件包括： 1. **多核导航器**：这是一个基于包的管理器，拥有16k队列，可以硬件加速任务调度，将任务分配到合适的可用硬件上，提高了系统效率。 2. **TeraNet**：这是一个2-Tbps容量的交换中心资源，利用包交换技术来移动数据包，确保了高数据传输速率。 3. **多核共享内存控制器(MSMC)**：允许处理核心直接访问共享内存，不占用TeraNet的带宽，防止内存访问阻塞数据包移动，增强了系统的并发性能。 4. **HyperLink**：提供了一种50-Gbaud的芯片级互连，使得SoC能够协同工作。它的低协议开销和高吞吐量使其成为芯片间连接的理想接口，与多核导航器配合，能透明地调度任务到串联设备，使任务执行如同在本地资源上运行一样高效。 TCI6636K2H是基于KeyStone II架构的多核DSP+ARM系统级芯片，具体特性包括： - 八个TMS320C66x DSP核心子系统（每个带有1.0GHz或1.2GHz的C66x固定/浮点DSP核心），提供38.4 GMacs（固定点）和19.2 GFlops（浮点）的处理能力。 - 四个ARM Cortex-A15 MPCore处理器，最高可运行在1.4GHz，共享4MB L2缓存，完全实现了ARMv7-A架构指令集。 - 多核共享内存控制器提供6MB的MSMSRAM，由八个DSP核心子系统和一个ARM核心子系统共享。这款芯片的设计考虑了安全性关键应用的需求，同时也提到了知识产权事项和其他重要免责声明。它适用于需要高性能计算和高效数据处理的场景，例如LTE调制解调器应用，能够在保持高速处理的同时，实现系统的低延迟和高效率。

SPRS835F—October 2013

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H

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2.1 C66x DSP CorePac

The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new

features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs

support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the

vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute

instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations.

Improved vector processing capability (each instruction can process multiple data in parallel) combined with the

natural instruction level parallelism of C6000 architecture (e.g., execution of up to 8 instructions per cycle) results

in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized

C/C++ compiler.

Each C66x DSP CorePac has two Rake and Search Accelerators (RSA) integrated on-chip. The tightly coupled

accelerator RSA can be used for:

• Chip rate spreading of WCDMA Rel’99, CDMA2000, HSDPA, and HSDPA+

• Chip rate despreading and correlation of WCDMA Rel’99, HSDPA, and HSDPA+ (e.g., Rake receiver,

preamble detection)

• Reed-Muller decoding

For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following

documents (2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19):

• C66x CPU and Instruction Set Reference Guide

• C66x DSP Cache User Guide

• C66x CorePac User Guide

JTAG BSDL_ID JTAGID Register (address location: 0x02620018)

0x0b98102f (PG 1.0)

0x1b98102f (PG 1.1)

Frequency

C66x Up to 1.2 GHz

ARM Cortex-A15 Up to 1.4 GHz

Voltage

Core (V) SmartReflex variable supply

I/O (V) 0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V, and 3.3 V

BGA Package 40 mm × 40 mm AAW 1517-pin flip-chip plastic BGA

Process Technology μm 0.028 μm

Product Status

(3)

Product Preview (PP), Advance Information (AI),

or Production Data (PD)

End of Table 2-1

1 The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details

2 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.

3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Table 2-1 Characteristics of the TCI6636K2H Processor (Part 2 of 2)

HARDWARE FEATURES TCI6636K2H

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS835F—October 2013

TCI6636K2H

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2.2 ARM CorePac

The ARM CorePac of the TCI6636K2H integrates an ARM Cortex-A15 Cluster (4 ARM Cortex-A15 processors)

with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements.

The ARM Cortex-A15 processor is an ARMv7A-compatible, dual-issue, out-of-order pipeline with integrated L1

caches. The implementation also supports advanced SIMDV2 (Neon technology) and VFPv4 (Vector Floating

Point) architecture extensions, security, virtualization, LPAE (Large Physical Address Extension), and

multiprocessing extensions. The quad core cluster includes a 4MB L2 cache and support for AMBA4 AXI and AXI

Coherence Extension (ACE) protocols.

2.3 Development Tools

2.3.1 Development Support

In case the customer would like to develop their own features and software on the TCI6636K2H device, TI offers an

extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the

performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug

software and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of KeyStone devices:

• Software Development Tools:

– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools

– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software

needed to support any DSP application

• Hardware Development Tools:

– Extended Development System (XDS™) Emulator (supports multiprocessor system debug)

– EVM (Evaluation Module)

2.3.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and

support tools. Each family member has one of two prefixes: X or [blank]. These prefixes represent evolutionary

stages of product development from engineering prototypes through fully qualified production devices/tools.

Device development evolutionary flow:

• X: Experimental device that is not necessarily representative of the final device's electrical specifications

• [Blank]: Fully qualified production device

Support tool development evolutionary flow:

• X: Development-support product that has not yet completed Texas Instruments internal qualification testing.

• [Blank]: Fully qualified development-support product

Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the following

disclaimer:

Developmental product is intended for internal evaluation purposes.

Fully qualified and production devices and development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS835F—October 2013

TCI6636K2H

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2.4 Related Documentation from Texas Instruments

These documents describe the TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC). Copies of

these documents are available on the Internet at www.ti.com.

64-bit Timer (Timer 64) for KeyStone Devices User Guide SPRUGV5

ARM CorePac User Guide for KeyStone II Devices User Guide SPRUHJ4

Antenna Interface 2 (AIF2) for KeyStone Devices User Guide SPRUGV7

AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone Devices SPRABH8

Bit Coprocessor (BCP) for KeyStone Devices User Guide SPRUGZ1

BCP-TCP3d for KeyStone Devices SPRABH6

Bootloader for the C66x DSP User Guide SPRUGY5

C66x CorePac User Guide SPRUGW0

C66x CPU and Instruction Set Reference Guide SPRUGH7

C66x DSP Cache User Guide SPRUGY8

Chip Interrupt Controller (CIC) for KeyStone Devices User Guide SPRUGW4

Connecting AIF2 with FFTC SPRABF3

Debug and Trace for KeyStone Devices User Guide SPRUGZ2

DDR3 Memory Controller for KeyStone Devices User Guide SPRUGV8

DSP Power Consumption Summary for KeyStone Devices SPRABL4

External Memory Interface (EMIF16) for KeyStone Devices User Guide SPRUGZ3

Emulation and Trace Headers Technical Reference SPRU655

Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide SPRUGS5

Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide SPRUGS2

General Purpose AIF2 Traffic for KeyStone Devices SPRABH3

General Purpose Input/Output (GPIO) for KeyStone Devices User Guide SPRUGV1

Gigabit Ethernet (GbE) Switch Subsystem (1 GB) for KeyStone Devices User Guide SPRUGV9

HyperLink for KeyStone Devices User Guide SPRUGW8

Inter Integrated Circuit (I

C) for KeyStone Devices User Guide SPRUGV3

Interrupt Controller (INTC) for KeyStone Devices User Guide SPRUGW4

Memory Protection Unit (MPU) for KeyStone Devices User Guide SPRUGW5

Multicore Navigator for KeyStone Devices User Guide SPRUGR9

Multicore Shared Memory Controller (MSMC) for KeyStone II Devices User Guide SPRUHJ6

Multicore Programming Guide SPRAB27

Network Coprocessor (NETCP) for KeyStone Devices User Guide SPRUGZ6

Optimizing Application Software on KeyStone Devices SPRABG8

Optimizing Loops on the C66x DSP SPRABG7

Packet Accelerator (PA) for KeyStone Devices User Guide SPRUGS4

Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide SPRUGS6

Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide SPRUGV2

Power Sleep Controller (PSC) for KeyStone Devices User Guide SPRUGV4

Security Accelerator (SA) for KeyStone Devices User Guide SPRUGY6

Security Addendum for KeyStone II Devices

(1)

SPRABS4

Semaphore2 Hardware Module for KeyStone Devices User Guide SPRUGS3

Serial Peripheral Interface (SPI) for KeyStone Devices User Guide SPRUGP2

Serial RapidIO (SRIO) for KeyStone Devices User Guide SPRUGW1

Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide SPRUGS0

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