Room temperature III–V nanolasers with
distributed Bragg reflectors epitaxially
grown on (001) silicon-on-insulators
YU HAN,
1,†
WAI KIT NG,
2,†
YING XUE,
1
KAM SING WONG,
2,3
AND KEI MAY LAU
1,4
1
Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon,
Hong Kong, China
2
Department of Physics and William Mong Institute of Nano Science and Technology, Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, Hong Kong, China
3
e-mail: phkwong@ust.hk
4
e-mail: eekmlau@ust.hk
Received 31 May 2019; revised 13 July 2019; accepted 30 July 2019; posted 30 July 2019 (Doc. ID 368995); published 27 August 2019
Efficient, scalable, bufferless, and compact III–V lasers directly grown on (001)-oriented silicon-on-insulators
(SOIs) are preferred light sources in Si-photonics. In this article, we present the design and operation of
III–V telecom nanolaser arrays with integrated distributed Bragg reflectors (DBRs) epitaxially grown on indus-
try-standard (001) SOI wafers. We simulated the mirror reflectance of different guided modes under various
mirror architectures, and accordingly devised nanoscale DBR gratings to support high refl ectivity around
1500 nm for the doughnut-shaped TE
01
mode. Building from InP/InGaAs nanoridges grown on SOI, we
fabricated subwavelength DBR mirrors at both ends of the nanoridge laser cavities and thus demonstrated
room-temperature low-threshold InP/InGaAs nanolasers with a 0.28 μm
2
cross-section and a 20 μm effective
cavity length. The direct growth of these bufferless nanoscale III–V light emitters on Si-photonics standard
(001) SOI wafers opens future options of fully integrated Si-based nanophotonic integrated circuits in the telecom
wavelength regime.
© 2019 Chinese Laser Press
https://doi.org/10.1364/PRJ.7.001081
1. INTRODUCTION
Epitaxial growth of III–V light emitters on (001)-oriented Si
substrates provides an intriguing alternative to the bonding ap-
proach for the realization of fully integrated Si-photonics chips
[1,2]. Such a monolithic integration scheme is compatible with
the currently scalable, high-yield, and cost-effective manufac-
turing process offered by electronics foundries. Recent studies
highlight the demonstration of room-temperature operation,
low threshold, and high reliability III–V laser diodes directly
grown on Si wafers using quantum dots as the active gain
medium and engineered III–V/Si templates for minimal dislo-
cation densities [3–5]. Using various defect trapping and filter-
ing techniques, the defect density of current III–V/Si templates
has been reduced to the order of 10
6
cm
−2
for GaAs on Si and
10
8
cm
−2
for InP on Si, respectively [6–8]. However, the sev-
eral micron thick III–V buffer needed for defect reduction
makes it difficult for the integration of the III–V light sources
with the Si waveguides underneath. While present research fo-
cuses on high-performance individual laser diodes grown on Si
substrates, future applications require efficient on-chip cou-
pling of III–V lasers with Si-based photonic and electronic
devices, and therefore necessitate bufferless III–V light emitters
directly grown on (001)-oriented SOI wafers [9].
Bufferless III–V nanostructures with various compositions
and architectures have been selectively grown on patterned
(001) Si and SOI substrates [10–18], and subsequently enabled
optically pumped nanoridge lasers with different emission
wavelengths [19–22]. Despite the subwavelength scale of the
cross-section of these nanolasers, the length of the nanocavities,
however, is usually longer than 50 μm to compensate for cavity
loss and sustain room temperature laser oscillation. This issue
aggravates at longer wavelengths, particularly in the strategically
important telecom bands, due to the increasing intrinsic and
mirror losses [23]. A cavity length of 100 μm is required to
support room-temperature O-band lasing inside suspended
InP/InGaAs nanocavities on bulk Si substrates [20]. The con-
tinuing miniaturization of the laser footprint improves the
integration density and reduces the power dissipation of
Si-based photonic integrated circuits [24–26]. Scaling down
the device dimension also opens new applications beyond op-
tical interconnects and data processing, such as sensing, medical
imaging, holography, and many more [27,28]. In contrast to
Research Article
Vol. 7, No. 9 / September 2019 / Photonics Research 1081
2327-9125/19/091081-06 Journal © 2019 Chinese Laser Press