2022 IEEE国际固态电路会议特刊：超低相位噪声X带BiCMOS VCO与数字PLL

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"JSSC 2022.12 - IEEE Journal of Solid-State Circuits" 这篇文章摘录自《IEEE Journal of Solid-State Circuits》（JSSC）2022年12月刊，这是一本专注于固态电路领域的权威学术期刊。JSSC是固态电路和系统设计领域的顶级出版物，它涵盖了微电子学、集成电路设计以及相关技术的最新研究和进展。编辑部在本期新增了两位副编辑，分别是D. Sylvester，他们的介绍位于3507页和3508页。这表明JSSC在不断更新其编辑团队，以保持与该领域发展的同步，确保发表的论文具有最高水平的科学严谨性和专业性。特别关注的是，本期还包含了一个关于2022年IEEE国际固态电路会议（ISSCC）的特辑。ISSCC是固态电路领域的旗舰会议，聚集了全球顶尖的研究成果，对推动该领域的发展起着至关重要的作用。W. Wu, H. Ito, J. Anders, A. Ali, 和 G. Pillonnet共同撰写的客座编辑序言位于3509页，为读者介绍了这个特辑的背景和价值。此外，本期还发表了多篇技术论文，涉及先进的电路设计： 1. "Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance"：Franceschin, Riccardi 和 Mazzanti的这篇论文详细探讨了利用串联谐振实现超低相位噪声的X波段双极型互补金属氧化物半导体（BiCMOS）压控振荡器（VCO）。VCO是射频和通信系统中的核心组件，其相位噪声性能直接影响系统的整体性能。 2. "A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector"：由Park, Hwang, Seong 和 Choi提交的这篇论文介绍了采用四倍时钟裕量相位选择器的低抖动环形压控振荡器（Ring-DCO）为基础的分数-N数字锁相环（PLL），并提出了一种降低分频计数器（DTC）范围的技术，旨在优化频率合成和减少时钟抖动。 3. "A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms Total-Integrated-Jitter and 1.56μs-Locking-Time"：Dartizio等人展示了一种基于Type-II齿轮切换和自适应频率切换的分数-N开关电荷泵（Bang-Bang PLL）设计，实现了极低的总集成抖动和快速的锁定时间，这对于高速数据传输和通信系统至关重要。 4. "A Harmonic-Mixing PLL Architecture"：最后，还有一篇关于谐波混合锁相环架构的论文，这类架构通常用于提高频率转换效率和线性度，对于现代无线通信和射频系统的设计至关重要。 JSSC 2022.12期揭示了固态电路领域的最新创新，包括高级振荡器设计、低抖动PLL技术以及谐波混合方法，这些都是推动未来电子设备小型化、高效化和高性能化的重要研究方向。

3518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 12, DECEMBER 2022

Fig. 6. Active core with the: (a) noise sources and (b) noise voltage PSDs

across the port of the active circuit at a different port current level.

When the resonator is connected to the active core, the port

current corresponds to the tank current I

Tank

= I

sin

(

)

. Thus,

the diodes are

OFF near the zero crossings of the tank current,

i.e., f o r |I

sin

(

)

| < V

/R or, equivalently, for −<θ <

and π − <θ<π+ , with

 = sin

−1





. (11)

Noticing that the noise PSD given by (10) is nonzero only for

−<θ<and π − <θ<π +, the effective noise

produced by the load resistors can now be computed again

using (6)

2π



2π

cos

(

)

n,X



dθ

2π







−

cos

(

)

dθ



. (12)

An approximated closed-form solution for the above integral

is found assuming small  [i.e., cos(θ) ≈ 1 in (12) and

 ≈ V

/(RI

) from (11)], a condition well-veriﬁed in practice,

leading to

≈ 2k

= 2k

(13)

where the last simpliﬁcation is made by replacing I

with (4).

Going ahead with other noise sources, the PSD contributed

by the extrinsic HBT base resistances is constant [gray dotted

curve in Fig. 6 (b)]. The noise voltage of each resistor R

, with

PSD of 4k

, is transferred from the base of each HBT to

the emitter, independently of the conduction state of D

and

(ON or OFF) and this yields a stationary noise across the

tank. Considering R

noise for both Q

and Q

, v

n,X



B−Q

1,2

2·4k

and the effective noise is readily calculated

B−Q

1,2

2π



2π

cos

(

)

· 2 · 4k

dθ= 4k

(14)

The green solid curves in Fig. 6(b) are the contribution

to the output noise from the collector shot-noise current

of Q

–Q

. The PSD of each noise current source, shown in

the schematic of Fig. 6(a), is i

n,Q1,2

= 2k

m1,2

is the

transconductance of Q

–Q

). From circuit analysis, assuming

high current gain of the transistors, the two noise current

sources produce an output noise voltage with PSD

n,X



1−2

T /g

+ 2 k

T /g

. Noticing that g

m1,2

= I

C1,2

(where

is the the rmal voltage, and I

= I

, I

= I

−I

,the

collector current of Q

and Q

, respectively), and that when

the active core drives the tank I

= I

Tank

(θ), using (6), the

effective noise is

1,2

2π



2π

cos

(

)

· 2k

×T



+ I

sin θ

− I

sin θ



dθ. (15)

A closed-form solution for (15) is found assuming the bias

current is equal to the peak tank current, I

= I

,which

is also the preferrable design choice to minimize the power

consumption. In this case,

1,2

= 4k

= 2k

(16)

with the right expression obtained by still replacing I

from (4).

If D

N,P

are implemented as diode-connected bipolar junction

transistors (BJT) (i.e., with base and collector shorted), their

primary noise contributions arise from the thermal noise of

the base resistances and the collector current shot noise.

Considerin g ﬁrst the base resistances, [violet dotted curves in

Fig. 6(b)], the thermal noise 4k

appears at the emitters

of Q

1,2

when one of the diodes turns on. Assuming an abrupt

turn-on, the noise PSD can be approximated with

n,X



B−D

N,P



> I

∗

0otherwise.

(17)

When the tank is connected to the active core, the port current

is I

Tank

= I

sin

(

)

is ON for <θ<π−  while D

FRANCESCHIN et al.: ULTRA-LOW PHASE NOISE X-BAND BiCMOS VCOs LEVERAGING THE SERIES RESONANCE 3519

is ON for π + <θ <2π − . Applying (6), the effective

noise is

B−D

N,P

2π



2π

cos

(

)

n,X



B−D

N,P

dθ

2π





π−



cos

(

)

dθ



≈ 2k



1 −



. (18)

The last expression is achieved solving the integral assuming

small  [i.e., approximating (11) with  ≈ V

/(RI

)]and

replacing I

from (4). Last, the violet solid curves in Fig. 6(b)

represent the noise PSD contributed by the shot noise of

the d iodes. Focusing on D

, it turns on when I

> I

∗

and in this situation, it can be modeled by an equivalent

resistance, r

= V

being the diode current) with

series voltage noise source with PSD v

n,D

= 2k

, due

to the collector shot noise. The output noise voltage due

to the D

shotnoise is then equal to the noise PSD at the

collectors of Q

1,2

. Considering the voltage divider formed

by r

and R/2, v

n,X





R/(R + r

)



n,D

. Assuming

abrupt turn on of D

, its current can be approximated as

= I

− I

∗

= I

− V

/R. When the active core drives

the resonator, with current I

Tank

(θ) = I

sin(θ), D

is ON for

<θ<π− with a current I

= I

Tank

(θ) − V

/R =

[sin(θ)− sin()]. Being the situation is symmetrical for D

the effective noise produced by the shot noise of two diodes

can be calculated with (6) as twice the effective noise of D

N,P

= 2

2π



π−



cos

(

)



R +

[sin θ −sin ]



·2k

[sin θ − sin ]

dθ. (19)

With some mathematical manipulations, and after replacing

from (4), (19) can be well-approximated by the following

closed-form expression:

N,P

≈ k

T ·R





+ 1



− 1



. (20)

Finally, the noise factor is found replacing (9), (13), (14), (16),

(18), and (20) in (8)

F =

+ N

B−Q

1,2

+ N

1,2

+ N

B−D

N,P

+ N

N,P

= 1 + 1+

+ 2k



1 −







+ 1



− 1



. (21)

The phase noise analysis is ﬁnally validated against simula-

tions, considering the oscillator design example introduced at

the end of Section II. The calculated total effective noise is

6.2 × 10

−20

/Hz, with the relative contributions of different

noise sources plotted in Fig. 7. The total effective noise

from simulations is 6.05 × 10

−20

/Hz, in good agreement

with calculations. The simulated relative noise contributions,

Fig. 7. Noise contribution: calculated versus simulated.

plotted in Fig. 7, are also in very good agreement with calcu-

lations. The noise factor estimated with (21) is F = 2.66, and

the phase noise at 1-MHz offset from the 10 -GHz oscillation

frequency, calculated with (5), is −141 dBc/Hz. Simulations

predict F = 2.58 and a phase noise of −141.1 dBc/Hz.

IV. 10-GH

Z SERIES-RESONANCE VCO DESIGNS

Two series-resonance VCOs at 10-GHz center frequency are

designed in a BiCMOS 55-nm technology. The ﬁrst design

targets the demonstration of an ultra-low phase noise, closing

the gap between VCOs in silicon and in compound semicon-

ductor technologies. In a second design, a different circuit

implementation for the resonator is investigated to enhance

the frequency tuning range and to trade phase noise for power

saving.

A. VCO1: Design for Ultra-Low Phase Noise

The circuit schematic of the 10-GHz VCO, designed to

prove an extremely low phase noise, is shown in Fig. 8.

Compared to the circuit introduced in Section II and shown

in Fig. 3, few modiﬁcations are introduced. To avoid wasting

voltage headroom and additional noise sources, the tail bias

currents d rawn in Fig. 3 are not implemented, while the dc

currents for Q

–Q

are sustained by the two inductors L

The dc base voltage of Q

–Q

is shifted down, with respect

to the collectors, introducing the coupling capacitors (C

)

and by applying the bias voltage V

through the choke

inductors, L

, realized as multiturn spirals with a n arrow-

width trace. The bias voltage V

is generated by the diode

of a current mirror (not shown), which sets the quiescent

current with a 1:12 mirror ratio. Q

–Q

are implemented as

36 parallel devices of 5 × 0.3 μm

. The total emitter area is

selected as a tradeoff between parasitic caps and noise from

the parasitic base resistance. The diodes D

, limiting

the voltage amplitude across the tank in stead y state, are

The two inductors L

, in parallel with the main tank, also introduce a

parallel resonance at lower frequency. But the ICNR characteristic of the

negative resistance circuit ensures the steady-state oscillation only at the series

resonance.

3520 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 12, DECEMBER 2022

Fig. 8. Schematic of the implemented 10-GHz series-resonance ultra-low

phase noise VCO.

realized with diode-connected HBTs.

Asmallandlow-Q

inductor L

(∼60 pH) feeds the supply voltage to Q

–Q

and resonates at 10 GHz with the parasitic capacitances at

the collectors of Q

–Q

. The equivalent resistance at the

collectors (R, drawn in grey in Fig. 8), required to have

negative resistance across the main resonator, is due to the

ﬁnite Q of L

and of the choke inductors L

. The tank,

connected at the emitters of Q

–Q

, is a series resonator

tuned at 10 GHz, with Q ∼ 20. The inductance, L

∼

0.9 nH, is realized as a single-turn spiral of 30-μm trace width,

symmetrically split in two parts, to host the tank capacitance in

the center, C

∼ 280 fF. The latter comprises two thick-oxide

accumulation-mode metal-oxide-semiconductor (AMOS) var-

actors in series with metal-oxide-metal (MOM) capacitors. The

tuning voltage is applied to the n-well of the varactors, while

the gate termina ls are biased at a constant voltage, V

1.5 V, through the compact choke inductors L

(sized such

that the equivalent parallel resistance is sufﬁciently higher than

the tank resistance at the series resonance). The differential

voltage at th e collectors of Q

–Q

, V

∗

, is in good approxima-

tion a square wave with amplitude limited by D

–D

to V

0.8 V. Due to the capacitive divider formed by C

with the

equivalent capacitance at the base of Q

, and the loading

of the tank to the transistors, the voltage across the resonator

follows V

∗

but with some attenuation: V

tank

= βV

∗

,where

from simulations, β ∼ 0.75. The fundamental component of

the voltage across the tank is re latively low, V

= (4/π)βV

≈

If the diodes are not used, the oscillation amplitude would be limited

by the core HBTs (Q

) forced to enter the saturation region. In this

situation, simulations point out a signiﬁcant phase noise penalty, due to a

larger contribution from the noise sources in Q

, including the noise of

the forward-biased collector–base junctions.

Fig. 9. VCO1 simulated noise contribution.

760 mV. However, the voltage on the series tank capacitor

is boosted by Q-times, thus reaching a peak value slightly

above 15 V.

Therefore, to avoid reliab ility issues, the tank capacitance is

implemented with the series of six capacitors (fo ur MOM caps

and two varactors). In this way, the voltage on each component

remains within the safe limits speciﬁed by the technology

for long-term reliability. The peak current in the resonator

is I

= V

≈ 220 mA. Therefore, to avoid transistors

turning off in th e oscillation cycle, the nominal dc current in

and Q

is set by V

to 250 mA. The supply voltage V

chosen equal to the minimum required to keep the transistors

operating in the active region, i.e., with V

> V

CEsat

≈ 0.4 V

CEsat

being the minimum collector-to-emitter voltage of the

HBT to operate in the active region). The differential voltages

at the collectors and at the emitters of Q

–Q

are out of phase

and with amplitude V

and βV

, respectively. Considering

the single-ended voltage amplitudes (i.e., half the differential

one), the minimum supply is V

CCmin

= (1 +β)V

/2 +

CEsat

= 1.2 V.

The simulated phase noise at 1-MHz offset from the 10 GHz

is −138 dBc/Hz, 3 dB higher than what simulated with the

idealized circuit in Fig. 3. The primary reason is the d ecreased

active power on the resonator due to the reduced tank voltage

swing. The attenuation of the tank voltage by β = 0.75 leads

to a phase noise increase of 10log(β

) = 2.5 dB. The other

0.5 dB is due to a slight increase of the noise factor, from F =

2.6 for the circuit in Fig. 3 to F = 2.95 in the ﬁnal design.

This noise factor is nevertheless comparable or even lower

than what achievable with parallel-tank oscillators, as it will be

conﬁrmed, in Section V, by compar ing the measured oscillator

FoM against previous works. Being the oscillator implemented

with bipolar transistors, the 1/ f

phase noise corner is below

1 kHz. The relative impact of the different noise sources at

1-MHz offset is plotted in Fig. 9. Comparing Fig. 7 with

Fig. 9, the tank noise contribution is reduced from ∼38% to

FRANCESCHIN et al.: ULTRA-LOW PHASE NOISE X-BAND BiCMOS VCOs LEVERAGING THE SERIES RESONANCE 3521

Fig. 10. Phase noise sensitivity to a variation of the load inductor L

and

inﬂuence on the oscillation frequency.

33% while biasing components, not considered in the analy sis,

contribute 3% of the total. Interestingly, simulations on the

implemented circuit point out also an increased contribution of

the noise from Q

–Q

and D

–D

which is almost completely

balanced by a reduced impact of the thermal noise of the

resistance R. The reduction of the noise contributed by R is

attributed to the presence of the resonator at the collectors of

1,2

, which prevents noise at the harmonics to be folded at the

oscillation frequency. Meanwhile, the (parasitic) capacitances

at the collectors of Q

1,2

sample the noise of Q

1,2

and D

N,P

when the diodes are ON and inject this noise into the tank

when the d iodes turn off, n ear the zero-crossing of the current,

i.e., at peaks of the ISF. As a result, the contribution of the

core HBTs and diodes to phase noise is increased. A rigorous

phase noise analysis to account for memory effects in the

active core becomes more complicated way. However, despite

the red istribution of the contributions in the active core, the

analysis on the circuit in Fig. 3 predicts reasonably well both

the noise factor and phase noise also for the implemented

circuit.

Finally, the sensitivity of phase noise to a variation of the

load inductor L

has been checked with simulations. Although

the impedance at th e collectors of Q

–Q

should be ideally

resistive, a condition met only at the resonance frequency

of L

with the stray capacitances, and simulations show that

the oscillator is robust to variations of L

(and hence of the

impedance magnitude and phase at the collectors of Q

1,2

).The

phase noise degradation, plotted in Fig . 10, remains below

0.5 and 1 dB, respectively, for L

within ±12% and ±18%

from the optimal value. The oscillation frequency, reported in

Fig. 10, is also mostly insensitive to L

, being changed by

only ±0.5% for L

variation of ∼±20%.

B. VCO2: Resonator Modiﬁed for Wider Tuning Range

The intrinsically high voltage on the capacitance of a

series resonator, Q-times the voltage across the tank, poses

a reliability issue due to the excessive voltage stress on the

components. Adding ﬁxed MOM capacitors in series to the

Fig. 11. (a) Schematic of the tank with wide tuning range and (b) equivalent

circuit near the series-resonance frequency.

varactors, as in the ﬁrst proposed design, unavoidably limits

the tank capacitance variation, ﬁnally penalizing the frequency

tuning range. To solve the issue, a different solution for

the resonator is investigated and implemented in a second

design of the series-resonance VCO. Looking at Fig. 11(a),

the oscillator active core, inside the rectangular box, is the

same as introduced in the ﬁrst design, but the tank is now

realized with an inductor, split into two parts (L

, L

),anda

variable capacitor (C

) directly connected across L

.Inthis

way, the tapped inductor works as a step-down transformer,

reducing the voltage across L

such that ﬁxed capacitors in

series to the varactors (to limit the voltage stress) are no more

required. Additionally, the grounded center tap of L

provides

a dc current path for the oscillator cor e, avoiding the need

for explicit dc-feed inductors (L

in Fig. 8) and thus reducing

silicon area occupation.

To gain further insight on the tank design, from network

analysis, the impedance seen across the two terminals of

the resonator shows parallel and series resonance, at angular

frequencies ω

and ω

, respectively, given by

√

,ω



. (22)

The ICNR characteristic of the active core guarantees that the

oscillation builds-up at the series resonance [ 38] where the

behavior of the network is the same of a simpler series tank,

shown in Fig. 11(b), formed by an equivalent inductance L

S−eq

and the capacitor C

coupled with an ideal n:1 transformer.

The transformer turns ratio, n, the equivalent inductance

S−eq

, and the quality factor of the equivalent resonator, Q

are determined by L

and L

, i.e., the position of the taps

along the implemented inductor. From network analysis

n =

+ L

(23)

S−eq

= L

n =

(

+ L

)(

n − 1

)

(24)

(

1 − n

)

+ nQ

(25)

where Q

and Q

are the quality factors of L

and L

3522 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 12, DECEMBER 2022

Fig. 12. Simulated impedance for the designed resonator and the equi valent

circuit valid near the series-resonance frequency.

Interestingly, if n > 2 (a condition which is satisﬁed to

scale the voltage on C

down to a safe value), the equiva-

lent resonator inductance L

S−eq

give n by (24) is larger than

the physical inductance (L

+ L

). This feature may prove

useful to design the oscillator with lower power consumption

without requiring an excessively large inductance. In fact,

if higher phase noise is acceptable, power consumption may be

reduced implementing the tank with a larger inductance (and

a smaller capacitance) to raise the equivalent tank resistance

and, according to (1), reduce the active power on the resonator.

However, with this design approach, silicon area increases.

Moreover, the decrease of the self-resonance frequency sets

an upper bound on maximum feasible inductor. The resonator

in Fig. 11(a) displays an equivalent inductance at its series

resonance which is larg er than the physically implemented

inductor, thus allowing to mitigate or circumvent the above

issue. The resonator is designed with L

= 370 pH and

= 180 pH giving, according to (23) and (24), n = 3and

S−eq

= 1.1 nH, twice the total implemented inductance of

+ L

= 550 pH. The variable capacitance C

is real-

ized with a bank of 15 digitally switched MOM capacitor s

for coarse frequency tuning and a small varactor for ﬁne

tuning. At its maximum value, C

= 2.34 pF, leading to

a series resonance frequency calculated with (22) of f

/2π ≈ 9.5 GHz. The plot in Fig. 12 compares the simulated

impedance of the implemented resonator (red curve) and the

impedance of the equivalent circuit (blue curve) with compo-

nents calculated with (23)–(25), proving a good agreement in

the neighborhood of the series resonance.

The tank quality factor, estimated with electromag-

netic (EM) simulation on the implemented layout, is Q = 17.

The slightly lower Q, compared to the tank in the ﬁrst VCO,

is due to the use of inductors of a smaller value and the

resistance of long parallel traces used to connect the large

tank capacitor. The tank equivalent resistance at the series

resonance is 4.06 . The simulated fundamental component

of the voltage across the tank is V

≈ 760 mV, as in the

ﬁrst designed VCO. With n = 3andQ = 17, the maximum

Fig. 13. Chip photograph: (a) VCO1 and (b) VCO2.

Fig. 14. Best and worst phase noises measured across the tuning range

(VCO1).

voltage across each capacitor is 2.1 V, sufﬁciently low not

to compromise the reliability. The simulated phase noise of

the VCO is −133 dBc/Hz at 1-MHz offset with a power

consumption of 330 mW from 1.2-V supply.

V. M

EASUREMENT RESULTS

The two designed VCOs have been realized in the BiCMOS

55 nm technology of STMicroelectronics and the chip photos

are shown in Fig. 13. First, measurements on VCO1 are

presented. Fig. 14 shows the phase noise versus the offset

frequency from the carrier, measured with a spectrum ana-

lyzer, in the best and worst case across the frequency tuning

range. The measurement at low offset frequency, up to nearly

100 kHz, is likely impaired by random walk noise of the

oscillator in free-run. The sp urs visible in the measurement

are likely due to a disturbance coupled through the supply or

the test board, not sufﬁciently suppressed. At 1-MHz offset,

the best phase noise is −138 dBc/Hz at 9.96-GHz oscilla-

tion frequency. The worst phase noise is −135.5 dBc/Hz at

10.2-GHz oscillation fr equency. The top plot in Fig. 15 shows

the spot phase noise at 1-MHz offset from the oscillation

frequency and the VCO FoM across the tuning range. The

power dissipation is 600 mW from 1.2-V supply, and the

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2022 IEEE国际固态电路会议特刊：超低相位噪声X带BiCMOS VCO与数字PLL

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