TI MSP430FR586x系列微控制器技术规格与特性

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"MSP430FR586x系列是TI公司生产的混合信号微控制器，包括MSP430FR5869、MSP430FR5868、MSP430FR5867、MSP430FR58671、MSP430FR5859、MSP430FR5858、MSP430FR5857、MSP430FR5849、MSP430FR5848、MSP430FR5847以及MSP430FR58471等型号。" MSP430FR58xx系列微控制器是Texas Instruments (TI)推出的一款高性能、超低功耗的微控制器，主要特点是其集成的铁电随机存取内存(FRAM)，这提供了高速写入能力和极高的耐用性。这些器件采用16位RISC架构，能够运行在高达16MHz的时钟频率，以实现高效的处理性能。该系列MCU的一大亮点在于其丰富的输入/输出(I/O)功能。所有端口都支持电容式触摸功能，而且无需外部组件，这对于设计简洁、节省成本的用户界面非常有帮助。此外，端口上还具备可编程的上拉和下拉电阻，以及在低功耗模式(LPM)下，可由边沿触发的唤醒功能。在功耗管理方面，MSP430FR58xx微控制器表现卓越。在工作模式下，电流消耗大约为100µA/MHz，而在待机模式(LPM3)下，电流仅为0.4µA（典型值）。进一步降低功耗的LPM4.5模式下，关断电流仅为0.02µA（典型值）。这些低功耗特性使其非常适合电池供电或能源受限的应用。通信接口方面，MSP430FR58xx系列支持多种协议，如增强型串行通信(eUSCI_A0和eUSCI_A1)、通用异步收发传输器(UART)、串行外设接口(SPI)以及I2C。其中，UART支持自动波特率检测，SPI速率最高可达10Mbps，I2C支持多个从设备寻址，而eUSCI_B0则提供SPI支持。在存储方面，MSP430FR58xx内置了64KB的非易失性FRAM，写入速度快，每个字的写入时间为125ns，64KB的数据能在4毫秒内写入完毕，且具有超过1015次的写入耐久性。此外，该系列微控制器的存储空间是统一标准的，程序、数据和存储共享同一空间。智能数字外设包括一个32位硬件乘法器(MPY)，以及低功耗低频内部时钟源(VLO)和10个可选的厂家调整频率的定频数控振荡器(DCO)，确保了灵活的时钟系统管理。 MSP430FR58xx系列微控制器适用于需要高效能、低功耗、以及强大I/O和通信能力的嵌入式应用，比如工业控制、消费电子、物联网(IoT)设备和便携式设备。其独特的FRAM技术、强大的通信功能和出色的电源管理特性使其成为许多领域设计者的首选。

MSP430FR5869

MSP430FR5868

MSP430FR5867

MSP430FR58671

MSP430FR5859

MSP430FR5858

MSP430FR5857

MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471

ZHCSCI4C –MAY 2014 –REVISED MARCH 2015

www.ti.com.cn

5 Specifications

5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at DVCC and AVCC pins to V

–0.3 4.1 V

Voltage difference between DVCC and AVCC pins

(2)

±0.3 V

+ 0.3 V

Voltage applied to any pin

(3)

–0.3 V

(4.1 Max)

Diode current at any device pin ±2 mA

Storage temperature, T

stg

(4)

–40 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous

writes to RAM and FRAM.

(3) All voltages referenced to V

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±1000

(ESD)

Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22-C101

(2)

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

Typical data are based on V

= 3.0 V, T

= 25°C unless otherwise noted.

MIN NOM MAX UNIT

Supply voltage range applied at all DVCC and AVCC

1.8

(4)

3.6 V

pins

(1) (2) (3)

Supply voltage applied at all DVSS and AVSS pins 0 V

Operating free-air temperature -40 85 °C

Operating junction temperature -40 85 °C

DVCC

Capacitor value at DVCC

(5)

-20%

µF

No FRAM wait states

0 8

(7)

(NWAITSx = 0)

SYSTEM

Processor frequency (maximum MCLK frequency)

(6)

MHz

With FRAM wait states

0 16

(9)

(NWAITSx = 1)

(8)

ACLK

Maximum ACLK frequency 50 kHz

SMCLK

Maximum SMCLK frequency 16

(9)

MHz

(1) It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device

operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.

Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

(2) See 表 5-1 for additional important information.

(3) Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet.

(4) The minimum supply voltage is defined by the supervisor SVS levels. See 表 5-2 for the exact values.

(5) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin.

(6) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

(7) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted.

(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed

without wait states.

(9) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted. If a clock sources with a larger

typical value is used, the clock must be divided in the clock system.

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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859

MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471

MSP430FR5869

MSP430FR5868

MSP430FR5867

MSP430FR58671

MSP430FR5859

MSP430FR5858

MSP430FR5857

MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471

www.ti.com.cn

ZHCSCI4C –MAY 2014–REVISED MARCH 2015

5.4 Active Mode Supply Current Into V

Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)

(1) (2)

FREQUENCY (f

MCLK

= f

SMCLK

)

1 MHz 4 MHz 8 MHz 12 MHz 16 MHz

EXECUTION

PARAMETER V

0 wait states 0 wait states 0 wait states 1 wait states 1 wait states UNIT

MEMORY

(NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 1) (NWAITSx = 1)

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

AM, FRAM_UNI

FRAM 3.0 V 210 640 1220 1475 1845 µA

(Unified memory)

(3)

FRAM

AM, FRAM

(0%)

(4) (5)

0% cache hit 3.0 V 370 1280 2510 2080 2650 µA

ratio

FRAM

AM, FRAM

(50%)

(4) (5)

50% cache hit 3.0 V 240 745 1440 1575 1990 µA

ratio

FRAM

AM, FRAM

(66%)

(4) (5)

66% cache hit 3.0 V 200 560 1070 1300 1620 µA

ratio

FRAM

AM, FRAM

(75%)

(4) (5)

75% cache hit 3.0 V 170 255 480 890 1085 1155 1310 1420 1620 µA

ratio

FRAM

AM, FRAM

(100%

(4) (5)

100% cache hit 3.0 V 110 235 420 640 730 µA

ratio

AM, RAM

(6)

RAM 3.0 V 130 320 585 890 1070 µA

AM, RAM only

(7) (5)

RAM 3.0 V 100 180 290 555 860 1040 1300 µA

(1) All inputs are tied to 0 V or to V

. Outputs do not source or sink any current.

(2) Characterized with program executing typical data processing.

ACLK

= 32768 Hz, f

MCLK

= f

SMCLK

= f

DCO

at specified frequency, except for 12 MHz. For 12 MHz, f

DCO

= 24 MHz and

MCLK

= f

SMCLK

= f

DCO

/2.

At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency

MCLK,eff

) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait

states or the cache hit ratio.

The following equation can be used to compute f

MCLK,eff

= f

MCLK

/ [wait states × (1 - cache hit ratio) + 1]

For example, with 1 wait state and 75% cache hit ratio f

MCKL,eff

= f

MCLK

/ [1 × (1 - 0.75) + 1] = f

MCLK

/ 1.25.

(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.

(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit

ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of

every four accesses is from cache, and the remaining are FRAM accesses.

(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best

linear fit using the typical data shown in Section 5.4.

(6) Program and data reside entirely in RAM. All execution is from RAM.

(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859

MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471

MSP430FR5869

MSP430FR5868

MSP430FR5867

MSP430FR58671

MSP430FR5859

MSP430FR5858

MSP430FR5857

MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471

www.ti.com.cn

ZHCSCI4C –MAY 2014–REVISED MARCH 2015

5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V

) Excluding External

Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

-40 °C 25 °C 60 °C 85°C

PARAMETER V

UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

2.2 V 0.5 0.9 2.2 6.1

Low-power mode 2, 12-pF

LPM2,XT12

μA

crystal

(2) (3) (4)

3.0 V 0.5 0.9 1.8 2.2 6.1 17

2.2 V 0.5 0.9 2.2 6.0

Low-power mode 2, 3.7-pF

LPM2,XT3.7

μA

cyrstal

(2) (5) (4)

3.0 V 0.5 0.9 2.2 6.0

2.2 V 0.3 0.7 1.9 5.8

Low-power mode 2, VLO,

LPM2,VLO

μA

includes SVS

(6)

3.0 V 0.3 0.7 1.6 1.9 5.8 16.7

Low-power mode 3, 12-pF 2.2 V 0.5 0.6 0.9 1.85

LPM3,XT12

crystal, excludes SVS

(2) (3)

μA

3.0 V 0.5 0.6 0.9 0.9 1.85 4.9

(7)

Low-power mode 3, 3.7-pF 2.2 V 0.4 0.5 0.8 1.7

cyrstal, excludes SVS

(2) (5)

LPM3,XT3.7

μA

(8)

3.0 V 0.4 0.5 0.8 1.7

(also refer to Figure 5-2)

2.2 V 0.3 0.4 0.7 1.6

Low-power mode 3,

LPM3,VLO

μA

VLO, excludes SVS

(9)

3.0 V 0.3 0.4 0.7 0.7 1.6 4.7

Low-power mode 4, includes 2.2 V 0.4 0.5 0.8 1.7

LPM4,SVS

SVS

(10)

μA

3.0 V 0.4 0.5 0.8 0.8 1.7 4.8

(also refer to Figure 5-3)

2.2 V 0.2 0.3 0.6 1.5

Low-power mode 4,

LPM4

μA

excludes SVS

(11)

3.0 V 0.2 0.3 0.6 0.6 1.5 4.6

(1) All inputs are tied to 0 V or to V

. Outputs do not source or sink any current.

(2) Not applicable for devices with HF crystal oscillator only.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5-pF load.

(4) Low-power mode 2, crystal oscillator test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),

XT1

= 32768 Hz, f

ACLK

= f

XT1

, f

MCLK

= f

SMCLK

= 0 MHz

(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen

to closely match the required 3.7-pF load.

(6) Low-power mode 2, VLO test conditions:

Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included.

CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),

XT1

= 0 Hz, f

ACLK

= f

VLO

, f

MCLK

= f

SMCLK

= 0 MHz

(7) Low-power mode 3, 12-pF crystal, excludes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled

(SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

XT1

= 32768 Hz, f

ACLK

= f

XT1

, f

MCLK

= f

SMCLK

= 0 MHz

(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled

(SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

XT1

= 32768 Hz, f

ACLK

= f

XT1

, f

MCLK

= f

SMCLK

= 0 MHz

(9) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is

disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

XT1

= 0 Hz, f

ACLK

= f

VLO

, f

MCLK

= f

SMCLK

= 0 MHz

(10) Low-power mode 4, includes SVS test conditions:

Current for brownout and SVS are included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),

XT1

= 0 Hz, f

ACLK

= 0 Hz, f

MCLK

= f

SMCLK

= 0 MHz

(11) Low-power mode 4, excludes SVS test conditions:

Current for brownout is included. SVS is disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),

XT1

= 0 Hz, f

ACLK

= 0 Hz, f

MCLK

= f

SMCLK

= 0 MHz

Submit Documentation Feedback

Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859

MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471

MSP430FR5869

MSP430FR5868

MSP430FR5867

MSP430FR58671

MSP430FR5859

MSP430FR5858

MSP430FR5857

MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471

ZHCSCI4C –MAY 2014 –REVISED MARCH 2015

www.ti.com.cn

Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V

) Excluding External

Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

-40 °C 25 °C 60 °C 85°C

PARAMETER V

UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

Additional idle current if one

or more modules from Group

IDLE,GroupA

3.0V 0.02 0.33 1.3 μA

A (refer to 表 6-2) are

activated in LPM3 or LPM4.

Additional idle current if one

or more modules from Group

IDLE,GroupB

3.0V 0.015 0.25 1.0 μA

B (refer to 表 6-2) are

activated in LPM3 or LPM4

5.8 Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into V

) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

-40 °C 25 °C 60 °C 85°C

PARAMETER V

UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

2.2 V 0.4 0.45 0.5 0.7

Low-power mode 3.5, 12-pF

LPM3.5,XT12

μA

crystal, includes SVS

(2)(3)(4)

3.0 V 0.4 0.45 0.7 0.5 0.7 1.2

Low-power mode 3.5, 3.7-pF 2.2 V 0.2 0.25 0.3 0.45

LPM3.5,XT3.7

cyrstal, excludes SVS

(2)(5)(6)

μA

3.0 V 0.2 0.25 0.3 0.5

(also refer to Figure 5-4)

Low-power mode 4.5, 2.2 V 0.2 0.2 0.2 0.3

LPM4.5,SVS

includes SVS

(7)

μA

3.0 V 0.2 0.2 0.4 0.2 0.3 0.55

(also refer to Figure 5-5)

Low-power mode 4.5, 2.2 V 0.02 0.02 0.02 0.08

LPM4.5

excludes SVS

(8)

μA

3.0 V 0.02 0.02 0.02 0.08 0.35

(also refer to Figure 5-5)

(1) All inputs are tied to 0 V or to V

. Outputs do not source or sink any current.

(2) Not applicable for devices with HF crystal oscillator only.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5-pF load.

(4) Low-power mode 3.5, 12-pF crystal, includes SVS test conditions:

Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

XT1

= 32768 Hz, f

ACLK

= f

XT1

, f

MCLK

= f

SMCLK

= 0 MHz

(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen

to closely match the required 3.7-pF load.

(6) Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions:

Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

XT1

= 32768 Hz, f

ACLK

= f

XT1

, f

MCLK

= f

SMCLK

= 0 MHz

(7) Low-power mode 4.5, includes SVS test conditions:

Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

XT1

= 0 Hz, f

ACLK

= 0 Hz, f

MCLK

= f

SMCLK

= 0 MHz

(8) Low-power mode 4.5, excludes SVS test conditions:

Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

XT1

= 0 Hz, f

ACLK

= 0 Hz, f

MCLK

= f

SMCLK

= 0 MHz

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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859

MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471

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