AD7705/AD7706：2/3通道16位Σ-ΔADC功能与特性详解

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AD7705/AD7706是一系列由Analog Devices公司生产的高性能模拟信号数字化转换器（ADC）。这些单片集成器件是专为工业和消费电子应用设计的，具备显著的功能和特性。首先，AD7705有两个完全差分输入通道，而AD7706则提供三个伪差分输入通道，这使得它们非常适合于需要高精度、低噪声测量的应用，如音频信号处理、仪表读取或传感器数据采集。它们采用16位分辨率，这意味着每个输入信号可以被转换成16位数字表示，确保了极高的精度，且没有缺失代码，这对于信号处理的质量至关重要。非线性误差仅为0.003%，这意味着在全量程内，输出信号与理想线性关系之间的偏差非常小，这对于需要精确度的应用来说是个优势。集成的可编程增益前端允许用户根据需要调整输入信号的放大倍数，提供了从1到128的多种增益选项，为适应不同的信号强度提供了灵活性。数据传输接口设计独特，支持三种串行接口标准：SPI™（同步串行接口）、QSPI™（快速SPI）和MICROWIRE™，这些都是广泛应用于微控制器和数字信号处理器（DSP）平台的标准接口。此外，SCLK引脚上的施密特触发器输入功能有助于提高抗噪声性能，并且允许这些ADC在数据采集过程中缓冲模拟输入，增强系统的稳定性和可靠性。 AD7705/AD7706的工作电压范围宽，可以从2.7V到3.3V或4.75V到5.25V，这增加了它们在不同电源环境中的适应性。在功耗方面，最大功耗仅为1毫瓦（mW）在3V供电下，而在待机模式下，最大电流消耗为8毫安（mA），显示出其低功耗特性，适合电池供电设备。封装形式包括16引脚双列直插式（DIP）、16引脚小外形集成电路（SOIC）和薄型小外形封装（TSSOP），满足不同尺寸和散热需求的系统设计。AD7705/AD7706是一款功能强大、灵活多样的ADC解决方案，适用于对精度、速度和低功耗有严格要求的应用场景。

AD7705/AD7706

–6–

REV. A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input

to access serial data from the AD7705/AD7706. This serial clock can be a continuous clock

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-

tinuous clock with the information being transmitted to the AD7705/AD7706 in smaller

batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or

external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins.

Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK

OUT left unconnected. The part can be operated with clock frequencies in the range

500 kHz to 5 MHz.

3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected

between MCLK IN and MCLK␣ OUT. If an external clock is applied to MCLK IN, MCLK

OUT provides an inverted clock signal. This clock can be used to provide a clock source for

external circuitry and is capable of driving one CMOS load. If the user does not require it,

this MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures

that the part is not burning unnecessary power driving capacitive loads on MCLK OUT.

4 CS Chip Select. Active low Logic Input used to select the AD7705/AD7706. With this input

hard-wired low, the AD7705/AD7706 can operate in its three-wire interface mode with

SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the AD7705/AD7706.

5 RESET Logic Input. Active low input that resets the control logic, interface logic, calibration

coefficients, digital filter and analog modulator of the part to power-on status.

6 AIN2(+)[AIN1] AD7705: Positive input of the differential Analog Input Channel 2. AD7706: Analog Input

Channel 1.

7 AIN1(+)[AIN2] AD7705: Positive input of the differential Analog Input Channel 1. AD7706: Analog Input

Channel 2.

8 AIN1(–)[COMMON] AD7705: Negative input of the differential Analog Input Channel 1. AD7706: COMMON

Input. Analog inputs for Channels 1, 2 and 3 are referenced to this input.

9 REF IN(+) Reference Input. Positive input of the differential Reference Input to the AD7705/AD7706.

The reference input is differential with the provision that REF IN(+) must be greater than

REF IN(–). REF␣ IN(+) can lie anywhere between V

and GND.

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

SCLK

MCLK IN

MCLK OUT

RESET

AIN2(+)

AIN1(+)

AIN1(–)

GND

DIN

DOUT

DRDY

AIN2(–)

REF IN(–)

REF IN(+)

AD7705

TOP VIEW

(Not to Scale)

SCLK

MCLK IN

MCLK OUT

RESET

AIN1

AIN2

COMMON

GND

DIN

DOUT

DRDY

AIN3

REF IN(–)

REF IN(+)

AD7706

AD7705/AD7706

–7–REV. A

Pin No. Mnemonic Function

10 REF IN(–) Reference Input. Negative input of the differential reference input to the AD7705/AD7706.

The REF␣ IN(–) can lie anywhere between V

and GND provided REF␣ IN(+) is greater

than REF␣ IN(–).

11 AIN2(–)[AIN3] AD7705: Negative input of the differential analog Input Channel 2. AD7706: Analog Input

Channel 3.

12 DRDY Logic Output. A logic low on this output indicates that a new output word is available from

the AD7705/AD7706 data register. The DRDY pin will return high upon completion of a

read operation of a full output word. If no data read has taken place between output updates,

the DRDY line will return high for 500 × t

CLK␣ IN

cycles prior to the next output update.

While DRDY is high, a read operation should neither be attempted nor in progress to avoid

reading from the data register as it is being updated. The DRDY line will return low again

when the update has taken place. DRDY is also used to indicate when the AD7705/AD7706

has completed its on-chip calibration sequence.

13 DOUT Serial Data Output with serial data being read from the output shift register on the part. This

output shift register can contain information from the setup register, communications regis-

ter, clock register or data register, depending on the register selection bits of the Communica-

tions Register.

14 DIN Serial Data Input with serial data being written to the input shift register on the part. Data

from this input shift register is transferred to the setup register, clock register or communica-

tions register, depending, on the register selection bits of the Communications Register.

15 V

Supply Voltage, +2.7 V to +5.25 V operation.

16 GND Ground reference point for the AD7705/AD7706’s internal circuitry.

OUTPUT NOISE (5 V OPERATION)

Table I shows the AD7705/AD7706 output rms noise for the selectable notch and –3␣ dB frequencies for the part, as selected by FS0

and FS1 of the Clock Register. The numbers given are for the bipolar input ranges with a V

REF

of +2.5␣ V and V

= 5 V. These

numbers are typical and are generated at an analog input voltage of 0␣ V with the part used in either buffered or unbuffered mode. Table II

meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to note that

these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak

noise. The numbers given are for bipolar input ranges with a V

REF

of +2.5 V and for either buffered or unbuffered mode. These num-

bers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0.

Table I. Output RMS Noise vs. Gain and Output Update Rate @ 5 V

Filter First Typical Output RMS Noise in ␮V

Notch and O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of

Data Rate Frequency 1248163264128

MCLK IN = 2.4576 MHz

50␣ Hz 13.1␣ Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6

60␣ Hz 15.72␣ Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62

250␣ Hz 65.5␣ Hz 110 49 31 17 8 3.6 2.3 1.7

500␣ Hz 131␣ Hz 550 285 145 70 41 22 9.1 4.7

MCLK IN = 1 MHz

20␣ Hz 5.24␣ Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6

25␣ Hz 6.55␣ Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62

100␣ Hz 26.2␣ Hz 110 49 31 17 8 3.6 2.3 1.7

200␣ Hz 52.4␣ Hz 550 285 145 70 41 22 9.1 4.7

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