AR9341无线芯片技术详解

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"AR9341数据手册是Atheros Communications公司发布的一份技术文档，主要介绍了AR9341这款高性能、功能丰富的 IEEE 802.11n 2x2 2.4GHz 路由器芯片。这份数据手册详细描述了芯片的特性、功能以及在高级无线局域网平台中的应用。" AR9341 是一款针对高级WLAN平台设计的系统级芯片（SoC），主要特性包括： 1. **高性能无线标准支持**：AR9341遵循IEEE 802.11n标准，支持2x2 MIMO（多输入多输出）技术，能够提供高速的无线网络连接，最高理论传输速率可达300Mbps。 2. **2.4GHz频段**：该芯片工作在2.4GHz频段，这是家庭和商业环境中最常见的无线频段，可以兼容广泛的无线设备。 3. **高度集成**：AR9341集成了多种功能，如无线基带处理、射频前端、内存控制器以及处理器等，降低了系统复杂性和成本。 4. **MIPS处理器核心**：内嵌的MIPS处理器核心负责处理网络协议、安全算法和其他系统管理任务，确保高效运行。 5. **特色技术**：AR9341采用了Atheros的一些专有技术，例如Signal-Sustain Technology (SST) 用于提升无线信号的稳定性和穿透力，确保在复杂环境下的良好连接性能。 6. **安全性与认证**：芯片支持多种安全协议，如WPA、WPA2，确保无线网络的安全性。此外，它可能还包含了其他认证机制，如WPS，便于用户进行快速安全设置。 7. **电源管理**：考虑到路由器的长期运行，AR9341很可能具有优化的电源管理功能，以降低功耗并提高能效。 8. **兼容性与扩展性**：作为一款高端路由器芯片，AR9341应该具备良好的向下兼容性，能够支持802.11b/g标准，并可能支持最新的802.11ac或ax标准的升级。 9. **硬件改版应用**：由于标签提及“路由器硬改”，这意味着AR9341可能被爱好者和开发者用于自定义和升级路由器固件，以实现更高级的功能或优化性能。 AR9341是一款为高端路由器和无线接入点设计的高性能SoC，其强大的无线性能、高度集成和丰富的特性使其成为构建强大无线网络的理想选择。对于开发者和硬改爱好者来说，这款芯片提供了广阔的定制和优化空间。

PRELIMINARY

16 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.

16 • February 2011 COMPANY CONFIDENTIAL

2.4.1 CPU PLL

The CPU PLL is configured by the bit

CPU_PLL_CONFIG in “CPU DDR Clock

Control (CPU_DDR_CLOCK_CONTROL)”.

The clock can vary slightly by changing the

divider’s FRAC. The dithering is controlled

through the “CPU PLL Dither Parameter

(CPU_PLL_DITHER)” register. Note that if

DDR_CLK is derived from the CPU PLL, it is

better to turn off dithering.

The clock switcher and dynamic clock divider

guarantee any change in inputs to this module

is glitch-free; thus input to this block can

change. Make sure that, when modifying the

select to the clock switcher module, both clock

inputs are present as switching from one clock

to another depends on both clocks. Figure 2-4

details the derivation of the CPU_CLK that

clocks the MIPS processor.

2.4.2 DDR PLL

The DDR PLL is configured with “DDR PLL

Configuration (DDR_PLL_CONFIG)” and

“CPU DDR Clock Control

(CPU_DDR_CLOCK_CONTROL)”. The DDR

PLL clock is dithered by “CPU PLL Dither

Parameter (CPU_PLL_DITHER)”; it is done

immediately after issuing an auto refresh

command to the DDR. Figure 2-5 shows the

DDR_CLK and AHB_CLK select signal change

to clock switching logic, which should be made

only if both clock inputs are preset.

The FRAC part of the PLL is dynamic, but the

INT part of the divider requires the PWD to go

high and then low.

Thus, changing the PLL clocks dynamically

would be possible only by:

1. Asserting the PLL_BYPASS mode bit.

2. Asserting the PWD for that PLL.

3. Reconfiguring divider INT/FRAC values.

4. Waiting for the clock to become stable by

polling the UPDATE bit.

5. Removing the PLL_BYPASS bit for this PLL.

The CPU can do this procedure any time for

CPU_CLK/AHB_CLK, which is useful to

enter low power states leading to minimal

chip power consumption. Another way to

change the CPU/AHB/DDR_POST_DIV to

shift down to lower clock for these clocks.

An optimal DDR and CPU frequency can be

dynamically chosen, and the PLL

reprogrammed for optimal power.

However, make sure that no DDR

transaction is pending or in progress before

changing the DDR_CLK frequency.

Figure 2-4. 74Kc Processor CPU Clock

Figure 2-5. DDR_CLK and AHB_CLK

PRELIMINARY

18 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.

18 • February 2011 COMPANY CONFIDENTIAL

2.7 DDR Memory Controller

The AR9341 allows an external memory

interface supporting 16-bit SDRAM, 16-bit

DDR1, or DDR2. The memory controller can

enter DDR/SDRAM self refresh for low power

modes.

The SDRAM, DDR1, and DDR2 modes have

small differences in read/write transactions.

For a write transaction, DDR2 memory expects

write data after a latency depending on CAS

latency. DDR1 memory expects the first data

immediately after the clock in which the write

command is issued. SDRAM expects the write

data to start with the write command itself.

The controller uses the configurable parameter

DDR2_TWL in the “DDR2 Configuration

(DDR_DDR2_CONFIG)” register. The

parameter is applicable for DDR1 and DDR2

modes: it should be set to one for DDR1 mode,

and to (CAS – 1) * 2 – 1 for DDR2 mode.

The controller handles SDRAM mode as

needed depending on the “DDR Controller

Configuration (DDR_CTL_CONFIG)” register

SDRAM_MODE_EN bit.

On-Chip SRAM

The DDR controller provides 32 KBytes of on-

chip SRAM for access to critical information.

This SRAM is mapped at the base address

0x1D000000 and is accessible by CPU and all

other memory clients. The SRAM can be used

for critical control and data information

exchange between the CPU and memory

clients, when DDR memory is not accessible

during low power modes and during initial

boot from external hosts.

Enabling DDR1 Mode

Set the bit SDRAM_MODE_EN in “DDR2

Configuration (DDR_DDR2_CONFIG)” to

zero, and ENABLE_DDR2 to one.

HALF_WIDTH should be set to indicate x16

mode and VEC field in the register “DDR Read

Data Capture Bit Mask

(DDR_RD_DATA_THIS_CYCLE)” is required

to be set to 0xFFFF.

Enabling SDRAM Mode

Set SDRAM_MODE_EN in “DDR Controller

Configuration (DDR_CTL_CONFIG)”. Because

the 16-bit interface is only supported in this

mode, if this bit is set, HALF_WIDTH should

also be set, and the VEC bit in

“DDR Read Data Capture Bit Mask

(DDR_RD_DATA_THIS_CYCLE)” should be

set to 0xFFFF_FFFF.

2.7.1 DDR Configurations

Table 2-4 shows the DDR configurations.

Table 2-4. DDR Configurations

Device on Board Total Memory Mode DDR1 DDR2 Notes

512 Mbits x 16 64 MBytes 16 Bit Yes Yes CPU address A26/A27

unused

512 Mbits x 8

128 MBytes 16 Bit Yes No CPU address A27

unused

PRELIMINARY

Atheros Communications, Inc. AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC • 19

COMPANY CONFIDENTIAL February 2011 • 19

2.7.2 Address Mapping

Table 2-5 shows the correspondence of the

internal CPU address, the DDR interface

address, and the physical memory address.

Supported devices include:

■ DDR1/DDR2 512 Mbits x 16

■ DDR1 512 Mbits x 8

2.7.3 Refresh

DDR memory must refresh periodically. The

DDR controller has an automatic 25- or 40-

MHz refresh command generation module that

clocks with REF_CLK. Because DDR_CLK is

dynamic, the auto REFRESH_PERIOD works

on the fixed REF_CLK.

2.7.3.1 Self Refresh

The AR9341 DDR controller supports a self

refresh (SF) sequence; that is, it has hardware

support to issue commands to place DDR

memory into and to exit SF mode. The register

“DDR Self Refresh Control (DDR_SF_CTL)”

controls basic SF behavior.

If EN_SELF_REFRESH is set and no valid DDR

transactions are in progress, the DDR controller

initiates an SF enter sequence. If DDR clients

have transactions in progress, the controller

waits until no DDR activity is occurring.

If EN_AUTO_SF_EXIT is set, the controller

initiates an exit SF sequence upon detecting a

DDR request from any DDR client. If this bit is

not set, DDR is in SF, a DDR new request is

seen, the controller generates a miscellaneous

DDR_ACTIVITY_IN_SF interrupt (see the

(RST_MISC_INTERRUPT_STATUS)”).

Software can alternatively force the controller

to exit SF by setting EN_SELF_REFRESH to 0.

The “Self Refresh Timer (SF_TIMER)” register

bits SF_TIMER_RF_OUT_DPR_COUNT and

SF_TIMER_IN_RF_DPR_COUNT indicate the

REFRESH_PERIOD number that the controller

was in SF and the duration for which it was out

of SF. Using these variables, software can

decide when to enable hardware to reenter SF.

The controller can also generate an interrupt to

the CPU while entering SF, exiting SF, and

while in SF if DDR activity is detected.

Immediately after exiting SF, read commands

should not be issued until TXSR is met and

non-read commands should not be issued until

TXSNR is met. These timing parameters can be

programmed via the TXSNR and TXSR fields

of the DDR_SF_CTL registers. Note that these

are in terms of DDR_CLK and not REF_CLK.

While in SF, DDR_CK_P and DDR_CK_N

clocks can be gated, optionally using the

EN_SF_CLK_GATING bit.

Table 2-5. CPU Address: DDR Interface Address Mapping

DDR Interface Address Column Address: Bank Address: Row Address

[1]

DDR_A_0 0 — CPU_ADDR[11]

DDR_A_1 CPU_ADDR[2] — CPU_ADDR[12]

DDR_A_2 CPU_ADDR[3] — CPU_ADDR[13]

DDR_A_3 CPU_ADDR[4] — CPU_ADDR[14]

DDR_A_4 CPU_ADDR[5] — CPU_ADDR[15]

DDR_A_5 CPU_ADDR[6] — CPU_ADDR[16]

DDR_A_6 CPU_ADDR[7] — CPU_ADDR[17]

DDR_A_7 CPU_ADDR[8] — CPU_ADDR[18]

DDR_A_8 CPU_ADDR[23] — CPU_ADDR[19]

DDR_A_9 CPU_ADDR[25] — CPU_ADDR[20]

DDR_A_10 0 — CPU_ADDR[21]

DDR_A_11 CPU_ADDR[26] — CPU_ADDR[22]

DDR_A_12 CPU_ADDR[27] — CPU_ADDR[24]

DDR_BA_0

[2]

— CPU_ADDR[9] —

DDR_BA_1 — CPU_ADDR[10] —

[1]Row address: DDR_A_0 through DDR_A_12, when the row is accessed.

[2]The AR9341 does not support BA_2, which thus must be connected to GND at the memory if present.

PRELIMINARY

20 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.

20 • February 2011 COMPANY CONFIDENTIAL

2.8 SLIC

2.8.1 Overview

The AR9341 provides a single, 4-wired, multi-

channel PCM digital highway for connecting to

a SLIC-based VOIP interface circuit. The SLIC

interface is compatible with a standard PCM

interface based on T1 (24 channels at

1.544 MHz) or E1 (32 channels at 2.048 MHz).

Trunk interfaces are suitable for VOIP

applications. Other non-standard channel

numbers up to 64 channels and a bit rate up to

8.092 MHz are supported via register

configuration. In a VOIP application, the

AR9341 SLIC controller can be configured as a

bridge between the PCM voice interface and

the LAN/WAN/WLAN IP packet interface.

The SLIC controller can transmit/receive on 1,

2, or multiple-time multiplexed 8-bit voice

channels on the PCM trunk. Up to 64 channels

are supported through the bit mask channel

enable registers. All Tx/Rx operations are 8-bit

PCM samples transferred using descriptor-

based DMA controllers (mailboxes) between

the system memory and the trunk interface.

Each direction (Tx and Rx) has one mailbox

DMA controller.

The major features include:

■ Programmable number of SLIC_SLOTs

■ Enabling multiple slots

■ Master or slave programming

■ Short/long frame sync

■ Delayed or non-delayed data operation

mode

■ SLIC enable/disable

■ Programmable divider clock

■ 8-bits/slot (maximum of 64 slots); having 16

bits/slot requires enabling two consecutive

slots. In 16-bit mode, the total number of

slots available becomes 32.

■ Separate interrupts for Rx and Tx DMA

completion

■ SLIC interrupt for unexpected frame sync in

slave mode

■ Bit swap across byte boundary

■ Configurable options to send data at

various edges after frame sync

■ Variations in frame sync duration

– Frame sync can last for a half clock

duration of BIT_CLK

– Frame sync can stay for more than one

clock duration of BIT_CLK (the number

of clocks for which frame sync should be

high is configurable)

Figure 2-7 shows the SLIC block diagram.

2.8.2 SLIC Interface

The SLIC interface utilizes a versatile mailbox

DMA controller for all data transfers to and

from system Memory. See “Mailbox (DMA

Controller)” on page 33 for more information.

2.8.3 Transmit

In the Tx direction, software prepares suitable

voice buffers from IP packets received from

LAN/WAN/WLAN in system memory, and

hands to the mailbox DMA using descriptors.

The DMA controller reads the buffers from

memory and puts them onto the Tx channels or

time slots on the PCM interface. Only

channels/time slots enabled by the Tx mask

registers are used for sending Tx data. All Tx

data synchronizes with respect to frame sync,

which provides voice sample synchronization

between the source and the voice data receiver.

Channel numbering starts with respect to the

frame sync being asserted and based on

programmable number PCM clocks where

frame sync remains asserted.

2.8.4 Receive

In the Rx direction, the SLIC controller receives

voice samples from the channels/time slots

reenabled by the Rx mask register. These 8-bit

samples are then assembled and DMAed to

system memory based on the buffer pointers

provided in the Rx descriptors. Like Tx, all Rx

sample operations synchronize with respect to

frame sync. Channel numbering starts with

frame sync being asserted and is based on the

programmable number of PCM clocks where

frame sync remains asserted.

Figure 2-7. SLIC Block Diagram

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