KeyStone II DSP GbE Switch subsystem 用户指南

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"DSP Keystone2千兆网口数据手册提供了关于KeyStone II架构下的Gigabit Ethernet (GbE) Switch Subsystem的详细信息，适用于K2E和K2L设备。用户指南涵盖从架构到功能模块，以及时钟控制、内存映射等多个方面的内容。" 在了解DSP Keystone2千兆网口数据手册之前，我们首先需要知道Keystone II架构。Keystone是TI（Texas Instruments）公司推出的一种多核DSP平台，主要应用于通信、视频处理和工业自动化等领域。Keystone II是该系列的第二代产品，具有高性能、低功耗和高度集成的特点。 Gigabit Ethernet (GbE) Switch Subsystem是Keystone II DSP中的一个关键组件，它允许设备实现高速网络连接。手册中提到，该子系统符合行业标准，支持多种功能，包括时钟控制、流式包接口、媒体访问控制器子模块、接收FIFO架构等。时钟控制是网络子系统中至关重要的部分，手册详细介绍了几种关键的时钟，如Gigabit SwitchSubsystem Clock用于交换机操作；SGMII SerDes参考时钟，服务于SerDes（串行光收发器）接口；MDIO Clock用于管理数据接口；IEEE 1588 Time Synchronization Clock支持精确时间协议，确保网络中设备的时间同步；还有GMIIClock，通常用于与物理层设备的交互。内存映射部分讲述了GbE Switch如何在内存空间中分配资源，这对于理解如何通过内存访问和控制交换子系统至关重要。此外，流式包接口包括传输和接收两个方面，分别负责将数据包从主机发送到交换机以及从交换机接收数据包。媒体访问控制器（MAC）子模块是GbE通信的核心，负责数据的接收和发送操作。MAC接收FIFO架构设计用于处理流入的数据包，而优先级映射和传输VLAN优先级功能则确保了数据包的正确分类和优先级处理。统计子模块用于收集和记录网络活动相关的各种统计信息，这有助于故障排查和性能优化。例如，51页开始详细阐述了统计子模块的架构。 DSP Keystone2千兆网口数据手册提供了一个全面的视角来理解如何在Keystone II平台上实现高效的网络通信，涵盖了从底层硬件时钟到高层软件接口的每一个细节，对于开发者和系统工程师来说是一份非常宝贵的参考资料。

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3-26. MDIO Link Status Change Interrupt (Masked) Set Register (MDIO_LINKINTMASKSET) Field

Descriptions ............................................................................................................... 143

3-27. MDIO Link Status Change Interrupt (Masked) Clear Register (MDIO_LINKINTMASKCLR) Field

Descriptions ............................................................................................................... 144

3-28. MDIO User Command Complete Interrupt (Unmasked) Register (MDIO_USERINTRAW) Field

Descriptions ............................................................................................................... 145

3-29. MDIO User Command Complete Interrupt (Masked) Register (MDIO_USERINTMASKED) Field

Descriptions ............................................................................................................... 146

3-30. MDIO User Command Complete Interrupt Mask Set Register (MDIO_USERINTMASKSET) Field

Descriptions ............................................................................................................... 147

3-31. MDIO User Command Complete Interrupt Mask Clear Register (MDIO_USERINTMASKCLEAR) Field

Descriptions ............................................................................................................... 148

3-32. MDIO Manual Interface Register (MDIO_MANUAL_IF) Field Descriptions ...................................... 149

3-33. MDIO Manual Interface Register (MDIO_MANUAL_IF) Field Descriptions ...................................... 150

3-34. MDIO Poll Enable Register (MDIO_POLL_EN) Field Descriptions ............................................... 151

3-35. MDIO Clause Mode Register (MDIO_CLAUSE) Field Descriptions ............................................... 152

3-36. MDIO User Address Register 0 (MDIO_USERADDRESS0) Field Descriptions ................................. 153

3-37. MDIO User Address Register 1 (MDIO_USERADDRESS1) Field Descriptions ................................. 154

3-38. MDIO User Access Register 0 (MDIO_USERACCESS0) Field Descriptions .................................... 155

3-39. MDIO User PHY Select Register 0 (MDIO_USERPHYSEL0) Field Descriptions ............................... 156

3-40. MDIO User Access Register 1 (MDIO_USERACCESS1) Field Descriptions .................................... 157

3-41. MDIO User PHY Select Register 1 (MDIO_USERPHYSEL1) Field Descriptions ............................... 158

3-42. Ethernet Switch Submodules ........................................................................................... 159

3-43. Ethernet Switch Submodule Registers................................................................................. 160

3-44. GbE Switch Identification and Version Register (CPSW_IDVER) Field Descriptions ........................... 161

3-45. GbE Switch Control Register (CPSW_CONTROL) Field Descriptions ............................................ 162

3-46. Emulation Control Register (EM_CONTROL) Field Descriptions ................................................. 164

3-47. Statistics Port Enable Register (CPSW_STAT_PORT_EN) Field Descriptions ................................. 165

3-48. Priority Type Register (CPSW_PTYPE) Field Descriptions ........................................................ 166

3-49. Software Idle Register (CPSW_SOFT_IDLE) Field Descriptions .................................................. 167

3-50. Through Rate Register (CPSW_THRU_RATE) Field Descriptions ............................................... 168

3-51. Ethernet Port Short Gap Threshold Register (CPSW_GAP_THRESH) Field Descriptions .................... 169

3-52. FIFO Packet Transmit (Egress) Start Words Register (CPSW_TX_START_WDS) Field Descriptions ...... 170

3-53. Priority Based Flow Control Global Outflow Usage Threshold Set Register

(CPSW_TX_OUTFLOW_THRESH_SET) Field Descriptions ...................................................... 171

3-54. Priority Based Flow Control Global Outflow Usage Threshold Clear Register

(CPSW_TX_OUTFLOW_THRESH_CLR) Field Descriptions ...................................................... 172

3-55. Priority Based Flow Control Global Buffer Usage Threshold Set Low Register

(CPSW_TX_BUFFER_THRESH_SET_L) Field Descriptions ...................................................... 173

3-56. Priority Based Flow Control Global Buffer Usage Threshold Set High Register

(CPSW_TX_BUFFER_THRESH_SET_H) Field Descriptions ..................................................... 174

3-57. Priority Based Flow Control Global Buffer Usage Threshold Clear Low Register

(CPSW_TX_BUFFER_THRESH_CLR_L) Field Descriptions ...................................................... 175

3-58. Priority Based Flow Control Global Buffer Usage Threshold Clear High Register

(CPSW_TX_BUFFER_THRESH_CLR_H) Field Descriptions ..................................................... 176

3-59. Common Switch Port Submodule Registers (n = 0-4 for a 5 port switch or n = 0-8 for a 9 port switch)...... 177

3-60. Host Port 0 Specific Submodule Registers............................................................................ 179

3-61. Ethernet Port n Specific Submodule Registers (n = 1-4 for a 5 port switch or n = 1-8 for a 9 port switch)... 180

3-62. Port n Control Register (Pn_CONTROL) Field Descriptions ....................................................... 182

3-63. Port n FIFO Block Usage Count Register (Pn_BLK_CNT) Field Descriptions ................................... 183

3-64. Port n VLAN Register (Pn_PORT_VLAN) Field Descriptions ...................................................... 184

3-65. Port n Transmit Priority Mapping Register (Pn_TX_PRI_MAP) Field Descriptions ............................. 185

List of Tables SPRUHZ3A–August 2014–Revised April 2015

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3-66. Port 0 Priority Control Register (P0_PRI_CTL) Field Descriptions ................................................ 186

3-67. External Ethernet Port n Priority Control Register (Pn_PRI_CTL) Field Descriptions .......................... 187

3-68. Port n Receive Priority Mapping Register (Pn_RX_PRI_MAP) Field Descriptions .............................. 188

3-69. Port n Receive Frame Maximum Length Register (Pn_RX_MAXLEN) Field Descriptions ..................... 189

3-70. Port n Transmit Blocks Priority Register (Pn_TX_BLKS_PRI) Field Descriptions ............................... 190

3-71. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 0 (Pn_RX_DSCP_MAP0) Field Descriptions .. 191

3-72. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 1 (Pn_RX_DSCP_MAP1) Field Descriptions .. 192

3-73. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 2 (Pn_RX_DSCP_MAP2) Field Descriptions .. 193

3-74. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 3 (Pn_RX_DSCP_MAP3) Field Descriptions .. 194

3-75. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 4 (Pn_RX_DSCP_MAP4) Field Descriptions .. 195

3-76. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 5 (Pn_RX_DSCP_MAP5) Field Descriptions .. 196

3-77. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 6 (Pn_RX_DSCP_MAP6) Field Descriptions .. 197

3-78. Port n Receive IPv4/IPv6 DSCP Priority Mapping Register 7 (Pn_RX_DSCP_MAP7) Field Descriptions .. 198

3-79. Port n Receive Priority 0 Send Count Value Register (Pn_PRI0_SEND) Field Descriptions .................. 199

3-80. Port n Receive Priority 1 Send Count Value Register (Pn_PRI1_SEND) Field Descriptions .................. 200

3-81. Port n Receive Priority 2 Send Count Value Register (Pn_PRI2_SEND) Field Descriptions .................. 201

3-82. Port n Receive Priority 3 Send Count Value Register (Pn_PRI3_SEND) Field Descriptions .................. 202

3-83. Port n Receive Priority 4 Send Count Value Register (Pn_PRI4_SEND) Field Descriptions .................. 203

3-84. Port n Receive Priority 5 Send Count Value Register (Pn_PRI5_SEND) Field Descriptions .................. 204

3-85. Port n Receive Priority 6 Send Count Value Register (Pn_PRI6_SEND) Field Descriptions .................. 205

3-86. Port n Receive Priority 7 Send Count Value Register (Pn_PRI7_SEND) Field Descriptions .................. 206

3-87. Port n Receive Priority 0 Idle Count Value Register (Pn_PRI0_IDLE) Field Descriptions ..................... 207

3-88. Port n Receive Priority 1 Idle Count Value Register (Pn_PRI1_IDLE) Field Descriptions ..................... 208

3-89. Port n Receive Priority 2 Idle Count Value Register (Pn_PRI2_IDLE) Field Descriptions ..................... 209

3-90. Port n Receive Priority 3 Idle Count Value Register (Pn_PRI3_IDLE) Field Descriptions ..................... 210

3-91. Port n Receive Priority 4 Idle Count Value Register (Pn_PRI4_IDLE) Field Descriptions ..................... 211

3-92. Port n Receive Priority 5 Idle Count Value Register (Pn_PRI5_IDLE) Field Descriptions ..................... 212

3-93. Port n Receive Priority 6 Idle Count Value Register (Pn_PRI6_IDLE) Field Descriptions ..................... 213

3-94. Port n Receive Priority 7 Idle Count Value Register (Pn_PRI7_IDLE) Field Descriptions ..................... 214

3-95. Port n Transmit Destination Threshold Set Low Register (Pn_TX_DEST_THRESH_SET_L) Field

Descriptions ............................................................................................................... 215

3-96. Port n Transmit Destination Threshold Set High Register (Pn_TX_DEST_THRESH_SET_H) Field

Descriptions ............................................................................................................... 216

3-97. Port n Transmit Destination Threshold Clear Low Register (Pn_TX_DEST_THRESH_CLR_L) Field

Descriptions ............................................................................................................... 217

3-98. Port n Transmit Destination Threshold Clear High Register (Pn_TX_DEST_THRESH_CLR_H) Field

Descriptions ............................................................................................................... 218

3-99. Port n Global Transmit Buffer Threshold Set Low Register (Pn_TX_BUFFER_THRESH_SET_L) Field

Descriptions ............................................................................................................... 219

3-100. Port n Global Transmit Buffer Threshold Set High Register (Pn_TX_BUFFER_THRESH_SET_H) Field

Descriptions ............................................................................................................... 220

3-101. Port n Global Transmit Buffer Threshold Clear Low Register (Pn_TX_BUFFER_THRESH_CLR_L) Field

Descriptions ............................................................................................................... 221

3-102. Port n Global Transmit Buffer Threshold Clear High Register (Pn_TX_BUFFER_THRESH_CLR_H) Field

Descriptions ............................................................................................................... 222

3-103. Host Port 0 Source ID A Register (P0_SRC_ID_A) Field Descriptions ........................................... 223

3-104. Host Port 0 Source ID A Register (P0_SRC_ID_A) Field Descriptions ........................................... 224

3-105. Host Port 0 Host Blocks Priority Register (P0_HOST_BLKS_PRI) Field Descriptions ......................... 225

3-106. Ethernet Port n Transmit Destination Out Flow Add Values Low Register

(Pn_TX_DEST_OUTFLOW_ADDVAL_L) Field Descriptions ...................................................... 226

3-107. Ethernet Port n Transmit Destination Out Flow Add Values High Register

SPRUHZ3A–August 2014–Revised April 2015 List of Tables

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(Pn_TX_DEST_OUTFLOW_ADDVAL_H) Field Descriptions ...................................................... 227

3-108. Ethernet Port n Pause Frame Source Address Low Register (Pn_PAUSE_SA_L) Field Descriptions ....... 228

3-109. Ethernet Port n Pause Frame Source Address High Register (Pn_PAUSE_SA_H) Field Descriptions ..... 229

3-110. Ethernet Port n Time Sync Control Register (Pn_TS_CTL) Field Descriptions ................................. 230

3-111. Ethernet Port n Time Sync LTYPE and SEQ_ID_OFFSET Register (Pn_TS_SEQ_LTYPE) Field

Descriptions ............................................................................................................... 231

3-112. Ethernet Port n Time Sync VLAN LTYPE1 and VLAN LTYPE2 Register (Pn_TS_VLAN) Field

Descriptions ............................................................................................................... 232

3-113. Ethernet Port n Time Sync Control and LTYPE2 Register (Pn_TS_CTL_LTYPE2) Field Descriptions ...... 233

3-114. Ethernet Port n Time Sync Control 2 Register (Pn_TS_CTL2) Field Descriptions .............................. 234

3-115. Ethernet Port n MAC Control Register (Pn_MAC_CTL) Field Descriptions ...................................... 235

3-116. Ethernet Port n MAC Status Register (Pn_MAC_STATUS) Field Descriptions ................................. 237

3-117. Ethernet Port n MAC Soft Reset Register (Pn_MAC_SOFT_RESET) Field Descriptions ..................... 238

3-118. Ethernet Port n MAC Backoff Test Register (Pn_MAC_BACKOFF_TEST) Field Descriptions ............... 239

3-119. Ethernet Port n 802.3 Receive Pause Timer Register (Pn_MAC_RX_PAUSETIMER) Field Descriptions .. 240

3-120. Ethernet Port n Priority Flow Control Priority 0 Receive Pause Timer Register

(Pn_MAC_RX_PRI0_PAUSETIMER) Field Descriptions ........................................................... 241

3-121. Ethernet Port n Priority Flow Control Priority 1 Receive Pause Timer Register

(Pn_MAC_RX_PRI1_PAUSETIMER) Field Descriptions ........................................................... 242

3-122. Ethernet Port n Priority Flow Control Priority 2 Receive Pause Timer Register

(Pn_MAC_RX_PRI2_PAUSETIMER) Field Descriptions ........................................................... 243

3-123. Ethernet Port n Priority Flow Control Priority 3 Receive Pause Timer Register

(Pn_MAC_RX_PRI3_PAUSETIMER) Field Descriptions ........................................................... 244

3-124. Ethernet Port n Priority Flow Control Priority 4 Receive Pause Timer Register

(Pn_MAC_RX_PRI4_PAUSETIMER) Field Descriptions ........................................................... 245

3-125. Ethernet Port n Priority Flow Control Priority 5 Receive Pause Timer Register

(Pn_MAC_RX_PRI5_PAUSETIMER) Field Descriptions ........................................................... 246

3-126. Ethernet Port n Priority Flow Control Priority 6 Receive Pause Timer Register

(Pn_MAC_RX_PRI6_PAUSETIMER) Field Descriptions ........................................................... 247

3-127. Ethernet Port n Priority Flow Control Priority 7 Receive Pause Timer Register

(Pn_MAC_RX_PRI7_PAUSETIMER) Field Descriptions ........................................................... 248

3-128. Ethernet Port n 802.3 Transmit Pause Timer Register (Pn_MAC_TX_PAUSETIMER) Field Descriptions .. 249

3-129. Ethernet Port n Priority Flow Control Priority 0 Transmit Pause Timer Register

(Pn_MAC_TX_PRI0_PAUSETIMER) Field Descriptions ........................................................... 250

3-130. Ethernet Port n Priority Flow Control Priority 1 Transmit Pause Timer Register

(Pn_MAC_TX_PRI1_PAUSETIMER) Field Descriptions ........................................................... 251

3-131. Ethernet Port n Priority Flow Control Priority 2 Transmit Pause Timer Register

(Pn_MAC_TX_PRI2_PAUSETIMER) Field Descriptions ........................................................... 252

3-132. Ethernet Port n Priority Flow Control Priority 3 Transmit Pause Timer Register

(Pn_MAC_TX_PRI3_PAUSETIMER) Field Descriptions ........................................................... 253

3-133. Ethernet Port n Priority Flow Control Priority 4 Transmit Pause Timer Register

(Pn_MAC_TX_PRI4_PAUSETIMER) Field Descriptions ........................................................... 254

3-134. Ethernet Port n Priority Flow Control Priority 5 Transmit Pause Timer Register

(Pn_MAC_TX_PRI5_PAUSETIMER) Field Descriptions ........................................................... 255

3-135. Ethernet Port n Priority Flow Control Priority 6 Transmit Pause Timer Register

(Pn_MAC_TX_PRI6_PAUSETIMER) Field Descriptions ........................................................... 256

3-136. Ethernet Port n Priority Flow Control Priority 7 Transmit Pause Timer Register

(Pn_MAC_TX_PRI7_PAUSETIMER) Field Descriptions ........................................................... 257

3-137. Ethernet Port n MAC Emulation Control Register (Pn_MAC_EMCONTROL) Field Descriptions ............. 258

3-138. Ethernet Port n MAC Transmit Inter Packet Gap Register (Pn_MAC_TX_GAP) Field Descriptions ......... 259

3-139. Port Statistics Submodule Registers (n = 0-4 for a 5 port switch or n = 0-8 for a 9 port switch)............... 260

3-140. Port n Good Receive Frames Register (STATn_RXGOODFRAMES) Field Descriptions ..................... 264

3-141. Port n Broadcast Receive Frames Register (STATn_RXBROADCASTFRAMES) Field Descriptions ....... 265

3-142. Port n Multicast Receive Frames Register (STATn_RXMULTICASTFRAMES) Field Descriptions .......... 266

List of Tables SPRUHZ3A–August 2014–Revised April 2015

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3-143. Port n Pause Receive Frames Register (STATn_RXPAUSEFRAMES) Field Descriptions ................... 267

3-144. Port n Receive CRC Errors Register (STATn_RXCRCERRORS) Field Descriptions .......................... 268

3-145. Port n Receive Align/Code Errors Register (STATn_RXALIGNCODEERRORS) Field Descriptions ......... 269

3-146. Port n Oversized Receive Frames Register (STATn_RXOVERSIZEDFRAMES) Field Descriptions ........ 270

3-147. Port n Receive Jabber Frames Register (STATn_RXJABBERFRAMES) Field Descriptions ................. 271

3-148. Port n Undersized (Short) Receive Frames Register (STATn_RXUNDERSIZEDFRAMES) Field

Descriptions ............................................................................................................... 272

3-149. Port n Receive Fragment Frames Register (STATn_RXFRAGMENTS) Field Descriptions ................... 273

3-150. Port n ALE Drop Frames Register (STATn_ALE_DROP) Field Descriptions .................................... 274

3-151. Port n ALE Overrun Drop Frames Register (STATn_ALE_OVERRUN_DROP) Field Descriptions .......... 275

3-152. Port n Receive Octets Register (STATn_RXOCTETS) Field Descriptions ....................................... 276

3-153. Port n Good Transmit Frames Register (STATn_TXGOODFRAMES) Field Descriptions ..................... 277

3-154. Port n Broadcast Transmit Frames Register STATn_TXBROADCASTFRAMES) Field Descriptions ........ 278

3-155. Port n Multicast Transmit Frames Register (STATn_TXMULTICASTFRAMES) Field Descriptions .......... 279

3-156. Port n Pause Transmit Frames Register (STATn_TXPAUSEFRAMES) Field Descriptions ................... 280

3-157. Port n Deferred Transmit Frames Register (STATn_TXDEFERREDFRAMES) Field Descriptions .......... 281

3-158. Port n Transmit Frames Collision Register (STATn_TXCOLLISIONFRAMES) Field Descriptions ........... 282

3-159. Port n Transmit Frames Single Collision Register (STATn_TXSINGLECOLLFRAMES) Field Descriptions 283

3-160. Port n Transmit Frames Multiple Collision Register (STATn_TXMULTCOLLFRAMES) Field Descriptions . 284

3-161. Port n Transmit Excessive Collisions Register (STATn_TXECESSIVECOLLISIONS) Field Descriptions ... 285

3-162. Port n Transmit Late Collisions Register (STATn_TXLATECOLLISIONS) Field Descriptions ................ 286

3-163. Port n Transmit Carrier Sense Errors Register (STATn_TXCARRIERSENSEERRORS) Field

Descriptions ............................................................................................................... 287

3-164. Port n Transmit Octets Register (STATn_TXOCTETS) Field Descriptions ...................................... 288

3-165. Port n Receive and Transmit 64 Octet Frames Register (STATn_64OCTETFRAMES) Field Descriptions . 289

3-166. Port n Receive and Transmit 65-127 Octet Frames Register (STATn_65T127OCTETFRAMES) Field

Descriptions ............................................................................................................... 290

3-167. Port n Receive and Transmit 128-255 Octet Frames Register (STATn_128T255OCTETFRAMES) Field

Descriptions ............................................................................................................... 291

3-168. Port n Receive and Transmit 256-511 Octet Frames Register (STATn_256T511OCTETFRAMES) Field

Descriptions ............................................................................................................... 292

3-169. Port n Receive and Transmit 512-1023 Octet Frames Register (STATn_512T1023OCTETFRAMES)

Field Descriptions ........................................................................................................ 293

3-170. Port n Receive and Transmit 1024 and Up Octet Frames Register (STATn_1024TUPOCTETFRAMES)

Field Descriptions ........................................................................................................ 294

3-171. Port n Net Octets Register (STATn_NETOCTETS) Field Descriptions ........................................... 295

3-172. Port n Receive Bottom of FIFO Drop Register (STATn_RX_BOTTOM_FIFO_DROP) Field Descriptions .. 296

3-173. Port n Port Mask Drop Register (STATn_PORTMASK_DROP) Field Descriptions ............................ 297

3-174. Port n Receive Top of FIFO Drop Register (STATn_RX_TOP_FIFO_DROP) Field Descriptions ............ 298

3-175. Port n Receive Top of FIFO Drop Register (STATn_ALE_RATE_LIMIT_DROP) Field Descriptions ........ 299

3-176. Port n ALE VLAN ID Ingress Check Drop Register (STATn_ALE_VID_INGRESS_DROP) Field

Descriptions ............................................................................................................... 300

3-177. Port n ALE Destination Equals Source Drop Register (STATn_ALE_DA_EQ_SA_DROP) Field

Descriptions ............................................................................................................... 301

3-178. Port n ALE Unknown Unicast Destination Register (STATn_ALE_UNKN_UNI) Field Descriptions .......... 302

3-179. Port n ALE Unknown Unicast Destination Byte Count Register (STATn_ALE_UNKN_UNI_BCNT) Field

Descriptions ............................................................................................................... 303

3-180. Port n ALE Unknown Multicast Destination Register (STATn_ALE_UNKN_MLT) Field Descriptions ........ 304

3-181. Port n ALE Unknown Multicast Destination Byte Count Register (STATn_ALE_UNKN_MLT_BCNT) Field

Descriptions ............................................................................................................... 305

3-182. Port n ALE Unknown Broadcast Destination Register (STATn_ALE_UNKN_BRD) Field Descriptions ...... 306

3-183. Port n ALE Unknown Broadcast Destination Byte Count Register (STATn_ALE_UNKN_BRD_BCNT)

SPRUHZ3A–August 2014–Revised April 2015 List of Tables

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Field Descriptions ........................................................................................................ 307

3-184. Port n Transmit Memory Protect Error Frames Register (STATn_TX_MEM_PROTECT_ERROR) Field

Descriptions ............................................................................................................... 308

3-185. Port n Transmit Priority m Frames Register (STATn_TX_PRIm) Field Descriptions ........................... 309

3-186. Port n Transmit Priority m Frames Byte Count Register (STATn_TX_PRIm_BCNT) Field Descriptions .... 310

3-187. Port n Transmit Priority m Drop Frames Register (STATn_TX_PRIm_DROP) Field Descriptions ........... 311

3-188. Port n Transmit Priority m Drop Frames Byte Count Register (STATn_TX_PRIm_DROP_BCNT) Field

Descriptions ............................................................................................................... 312

3-189. CPTS Registers ........................................................................................................... 313

3-190. CPTS Identification and Version Register (CPTS_IDVER) Field Descriptions .................................. 314

3-191. Time Sync Control Register (CPTS_CTL) Field Descriptions ...................................................... 315

3-192. RFTCLK Select Register (CPTS_RFTCLK_SEL) Field Descriptions ............................................. 316

3-193. Time Stamp Event Push Register (CPTS_TS_PUSH) Field Descriptions ....................................... 317

3-194. Time Stamp Load Value Register (lower 32 bits) (CPTS_TS_LOAD_VAL_L) Field Descriptions ............ 318

3-195. Time Stamp Load Enable Register (CPTS_TS_LOAD_EN) Field Descriptions ................................. 319

3-196. Time Stamp Comparison Value Register (lower 32 bits) (CPTS_TS_COMP_VAL_L) Field Descriptions ... 320

3-197. Time Stamp Comparison Length Register (CPTS_TS_COMP_LENGTH) Field Descriptions ................. 321

3-198. Interrupt Status Raw Register (CPTS_INTSTAT_RAW) Field Descriptions ..................................... 322

3-199. Interrupt Status Masked Register (CPTS_INTSTAT_MASKED) Field Descriptions ............................ 323

3-200. Interrupt Enable Register (CPTS_INT_ENABLE) Field Descriptions ............................................. 324

3-201. Event Pop Register (CPTS_EVENT_POP) Field Descriptions .................................................... 325

3-202. Event Information 0 Register (CPTS_EVENT_INFO0) Field Descriptions ....................................... 326

3-203. Event Information 1 Register (CPTS_EVENT_INFO1) Field Descriptions ....................................... 327

3-204. Event Information 2 Register (CPTS_EVENT_INFO2) Field Descriptions ....................................... 328

3-205. Event Information 3 Register (CPTS_EVENT_INFO3) Field Descriptions ....................................... 329

3-206. Time Stamp Load Value Register (upper 32 bits) (CPTS_TS_LOAD_VAL_H) Field Descriptions ........... 330

3-207. Time Stamp Comparison Value Register (upper 32 bits) (CPTS_TS_COMP_VAL_H) Field Descriptions .. 331

3-208. ALE Registers ............................................................................................................. 332

3-209. ALE Identification and Version Register (ALE_IDVER) Field Descriptions ....................................... 334

3-210. ALE Status Register (ALE_STATUS) Field Descriptions ........................................................... 335

3-211. ALE Control Register (ALE_CONTROL) Field Descriptions ....................................................... 336

3-212. ALE Prescale Register (ALE_PRESCALE) Field Descriptions .................................................... 338

3-213. ALE Aging Timer Register (ALE_AGING_TIMER) Field Descriptions ............................................ 339

3-214. ALE Unknown VLAN Register (UNKNOWN_VLAN) Field Descriptions .......................................... 340

3-215. ALE Table Control Register (ALE_TBLCTL) Field Descriptions ................................................... 341

3-216. ALE Table Word 2 Register (ALE_TBLW2) Field Descriptions .................................................... 342

3-217. ALE Table Word 1 Register (ALE_TBLW2) Field Descriptions .................................................... 343

3-218. ALE Table Word 0 Register (ALE_TBLW0) Field Descriptions .................................................... 344

3-219. ALE Port Control Register n (ALE_PORTCTLn) Field Descriptions .............................................. 345

3-220. ALE Unknown VLAN Member List Register (ALE_UNKN_VLAN_MBR_LIST) Field Descriptions ........... 346

3-221. ALE Unknown VLAN Unregistered Multicast Flood Mask Register

(ALE_UNKN_VLAN_UNREG_MLT_FLOOD) Field Descriptions .................................................. 347

3-222. ALE Unknown VLAN Registered Multicast Flood Mask Register

(ALE_UNKN_VLAN_REG_MLT_FLOOD) Field Descriptions ...................................................... 348

3-223. ALE Unknown VLAN Force Untagged Egress Register (ALE_UNKN_VLAN_FORCE_UNTAG_EGR)

Field Descriptions......................................................................................................... 349

3-224. ALE VLAN Mask Mux Select Register n (ALE_VLAN_MASK_MUXn) Field Descriptions ...................... 350

3-225. ECC Registers ............................................................................................................ 351

3-226. ECC Revision Register (ECC_REVISION) Field Descriptions...................................................... 352

3-227. ECC Module Vector Register (ECC_VECTOR) Field Descriptions ................................................ 353

List of Tables SPRUHZ3A–August 2014–Revised April 2015

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