LMK03328：超低抖动高性能时钟发生器

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"TI-LMK03328.pdf" 是TI公司的一款超低抖动高性能时钟发生器芯片的资料，主要特点包括内置两个独立的PLL（锁相环路）、八个输出通道以及集成的EEPROM。 TI的LMK03328是一款专为需要高精度时钟信号的系统设计的集成电路，它在确保极低的噪声和抖动性能的同时，提供了丰富的功能和灵活性。以下是该芯片的关键特性： 1. **超低噪声和高性能**： - 抖动性能卓越，当输出频率超过100MHz时，其典型值仅为100fs（均方根RMS），这确保了信号的高精度。 - 峰值信噪比(PSNR)达到-80dBc，表明它对电源噪声有很好的抑制能力，从而保证了信号质量。 2. **灵活的配置选项**： - 支持多达8个AC-LVPECL、AC-LVDS、AC-CML、HCSL或LVCMOS输出，用户可以根据需求选择不同的输出类型或组合。 - 提供多种工作模式，包括引脚模式、I2C模式和EEPROM模式。引脚模式通过硬件配置，I2C模式允许通过I2C总线进行动态配置，而EEPROM模式则允许预编程默认设置。 - 71个引脚中包含可选的预编程默认启动选项，简化了系统设计和配置。 3. **双路输入支持**： - 允许使用10MHz到52MHz的晶体振荡器输入，或者1MHz到300MHz的外部输入，适应不同频率源的需求。 - 自动或手动选择输入，增强了系统的灵活性。 4. **频率裕度调整**： - 可以使用低成本的可牵引晶振进行基准频率的精细调整，提供±50ppm的典型频率裕度。 - 输出分频器支持无毛刺脉冲的粗调频率裕度，进一步增加了设计的灵活性。 5. **其他特性**： - 内置电源管理，支持3.3V内核电源以及1.8V、2.5V、3.3V的输出电源。 - 工业级温度范围(-40°C至+85°C)，确保在各种环境条件下稳定工作。 - 封装采用7mm×7mm的48引脚WQFN，减小了板级空间需求。 6. **应用领域**： - LMK03328适用于需要精确时钟信号的系统，如交换机和路由器，这些设备通常需要高精度的时钟来同步数据传输和处理。 LMK03328是面向高性能通信和网络设备的理想时钟解决方案，它的低抖动、高灵活性和宽泛的工作范围使其在复杂系统中表现出色。结合I2C控制和内置EEPROM，可以实现更高级别的系统定制和优化。

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LMK03328

ZHCSE36D –AUGUST 2015–REVISED APRIL 2018

www.ti.com.cn

8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T

= –40°C to

85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input High Voltage 1.2 V

Input Low Voltage 0.6 V

Input High Current V

= VDD_DIG –40 40 µA

Input Low Current V

= GND –40 40 µA

Input Capacitance 2 pF

8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T

= –40°C to

85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input High Voltage 1.4 V

Input Mid Voltage 0.9 V

Input Low Voltage 0.4 V

Input High Current V

= VDD_DIG –40 40 µA

Input Low Current V

= GND –40 40 µA

Input Capacitance 2 pF

8.22 Analog Input Characteristics (GPIO[5])

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T

= –40°C to

85°C, pulldown resistor on GPIO[5] to GND as specified below, HW_SW_CTRL = 0

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ctrl

Control voltage range 0 VDD_DIG V

IN_XOOF

FSET_STEP

Input Voltage for XO

Frequency Offset Step

Selection on GPIO[5]

50 Ω to GND: Selects on-chip capacitive load set

by R88 and R89

50 mV

2.32 kΩ to GND: Selects on-chip capacitive load

set by R90 and R91

200 mV

5.62 kΩ to GND: Selects on-chip capacitive load

set by R92 and R93

400 mV

10.5 kΩ to GND: Selects on-chip capacitive load

set by R94 and R95

600 mV

18.7 kΩ to GND: Selects on-chip capacitive load

set by R96 and R97

800 mV

34.8 kΩ to GND: Selects on-chip capacitive load

set by R98 and R99

1000 mV

84.5 kΩ to GND: Selects on-chip capacitive load

set by R100 and R101

1200 mV

Left floating: Selects on-chip capacitive load set

by R102 and R103

1400 mV

DELAY

Delay between voltage

changes on GPIO[5] pin

100 ms

LMK03328

www.ti.com.cn

ZHCSE36D –AUGUST 2015 –REVISED APRIL 2018

(1) Total capacitive load for each bus line ≤ 400 pF.

(2) Ensured by design.

8.23 I

C-Compatible Interface Characteristics (SDA, SCL)

(1)(2)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T

= –40°C to

85°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input High Voltage 1.2 V

Input Low Voltage 0.6 V

Input Leakage –40 40 µA

Input Capacitance 2 pF

OUT

Input Capacitance 400 pF

Output Low Voltage I

= 3 mA 0.6 V

SCL

C Clock Rate 100 400 kHz

SU_STA

START Condition Setup Time SCL high before SDA low 0.6 µs

H_STA

START Condition Hold Time SCL low after SDA low 0.6 µs

PH_STA

SCL Pulse Width High 0.6 µs

PL_STA

SCL Pulse Width Low 1.3 µs

H_SDA

SDA Hold Time SDA valid after SCL low 0 0.9 µs

SU_SDA

SDA Setup Time 115 ns

R_IN

/ t

F_IN

SCL/SDA Input Rise and Fall

Time

300 ns

F_OUT

SDA Output Fall Time C

BUS

= 10 pF to 400 pF 250 ns

SU_STOP

STOP Condition Setup Time 0.6 µs

BUS

Bus Free Time between STOP

and START

1.3 µs

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Jitter specifications apply for differential output formats with low-jitter differential input clock or crystal input. Phase jitter measured with

Agilent E5052 signal source analyzer using a differential-to-single-ended converter (balun or buffer).

8.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics

(1)(2)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V, VDDO_x = 1.8 V, 2.5 V, 3.3 V, T

= 25°C, Reference Input = 50 MHz,

PFD = 100 MHz, Integer-N PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Post Divider = 8, Output Divider = 4, Output

Type = AC-LVPECL/AC-LVDS/AC-CML/HCSL/LVCMOS

PARAMETER OUTPUT TYPE UNIT

phn

10k

Phase noise at 10-kHz

offset

–143 –142 –142 –141 –139 dBc/Hz

phn

50k

Phase noise at 50-kHz

offset

–143.5 –143 –143 –142 –141 dBc/Hz

phn

100k

Phase noise at 100-kHz

offset

–144 –144 –144 –144 –143 dBc/Hz

phn

500k

Phase noise at 500-kHz

offset

–146 –146 –146 –146 –145 dBc/Hz

phn

Phase noise at 1-MHz

offset

–149.5 –149 –149 –149 –149 dBc/Hz

phn

Phase noise at 5-MHz

offset

–160.5 –160 –160 –159 –158 dBc/Hz

phn

20M

Phase noise at 20-MHz

offset

–164.5 –164 –164 –161 –159 dBc/Hz

Random Jitter integrated

from 10-kHz to 20-MHz

offsets

96 99 99 107 119 fs, RMS

LMK03328

ZHCSE36D –AUGUST 2015–REVISED APRIL 2018

www.ti.com.cn

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Jitter specifications apply for differential output formats with low-jitter differential input clock or crystal input. Phase jitter measured with

Agilent E5052 signal source analyzer using a differential-to-single-ended converter (balun or buffer).

8.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics

(1)(2)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V, VDDO_x = 1.8 V, 2.5 V, 3.3 V, T

= 25°C, Reference Input = 50 MHz,

PFD = 100 MHz, Fractional-N PLL bandwidth = 400 kHz, VCO Frequency = 5.15625 GHz, Post Divider = 8, Output Divider =

4, Output Type = AC-LVPECL/AC-LVDS/AC-CML/HCSL/LVCMOS

PARAMETER OUTPUT TYPE UNIT

phn

10k

Phase noise at 10-kHz

offset

–136 –136 –136 –135 –135 dBc/Hz

phn

50k

Phase noise at 50-kHz

offset

–139 –139 –139 –139 –139 dBc/Hz

phn

100k

Phase noise at 100-kHz

offset

–140 –140 –140 –140 –140 dBc/Hz

phn

500k

Phase noise at 500-kHz

offset

–142 –142 –142 –142 –142 dBc/Hz

phn

Phase noise at 1-MHz

offset

–150 –150 –150 –149 –149 dBc/Hz

phn

Phase noise at 5-MHz

offset

–160.5 –160 –160 –159 –158 dBc/Hz

phn

20M

Phase noise at 20-MHz

offset

–164.5 –164 –164 –161 –159 dBc/Hz

Random Jitter integrated

from 10-kHz to 20-MHz

offsets

120 122 122 130 136 fs, RMS

(1) Phase jitter measured with Agilent E5052 source signal analyzer using a differential-to single-ended converter (balun or buffer) for

differential outputs.

(2) Verified with crystals specified for a load capacitance of C

= 9 pF. PCB stray capacitance was measured to be 1 pF. Crystals tested:

19.44 MHz TXC (Part Number: 7M19472001), 25 MHz TXC (Part Number: 7M25072001), 38.88 MHz TXC (Part Number: 7M38872001).

(3) Refer to Parameter Measurement Information for relevant test conditions.

(4) For output frequency < 40 MHz, integration band for RMS phase jitter is 12 kHz – 5 MHz.

8.26 Closed-Loop Output Jitter Characteristics

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG= 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T

= –40°C to

85°C, Integer-N PLL with 4.8-GHz, 4.9152-GHz, 4.97664-GHz, 5-GHz or 5.1-GHz VCO, 400 kHz PLL bandwidth and doubler

enabled or disabled, Fractional-N PLL with 4.8-GHz, 4.9152-GHz, 4.944-GHz, 4.97664-GHz, 5-GHz, 5.15-GHz or 5.15625-

GHz VCO, 400-kHz bandwidth and doubler enabled or disabled, 1.8-V or 3.3-V LVCMOS output load of 2 pF to GND, AC-

LVPECL/AC-LVDS/CML output pair AC-coupled to 100-Ω differential load, HCSL outputs with 50 Ω || 2 pF to GND.

(1)(2)(3)(4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RMS Phase Jitter

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

19.2-MHz, 25-MHz, 27-MHz, 38.88-MHz

crystal, Integer-N PLL1 or PLL2, f

OUT

≥ 100

MHz, all differential output types

120 200 fs, RMS

RMS Phase Jitter

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

19.2-MHz, 25-MHz, 27-MHz, 38.88-MHz

crystal, Fractional-N PLL1 or PLL2, f

OUT

≥

100 MHz, all differential output types

200 350 fs, RMS

RMS Phase Jitter

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

50-MHz crystal, Integer-N PLL1 or PLL2,

OUT

= 156.25 MHz, all differential output

types

100 150 fs, RMS

RMS Phase Jitter

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

50-MHz crystal, Fractional-N PLL1 or

PLL2, f

OUT

= 155.52 MHz, all differential

output types

140 210 fs, RMS

RMS Phase Jitter

(12 kHz – 20 MHz)

(12 kHz – 5 MHz)

OUT

≥ 10 MHz, 1.8-V or 3.3-V LVCMOS

output, Integer-N or Fractional-N PLL1 or

PLL2

800 fs, RMS

LMK03328

www.ti.com.cn

ZHCSE36D –AUGUST 2015 –REVISED APRIL 2018

(1) Excludes oscilloscope sampling noise

8.27 PCIe Clock Output Jitter

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V, VDDO_x = 1.8 V, 2.5 V, 3.3 V, T

= 25°C, Reference Input = 25-MHz

crystal, OUT = 100-MHz HCSL

PARAMETER TEST CONDITIONS TYP PCle Spec UNIT

GEN3

PCIe Gen 3 Common Clock PCIe Gen 3 transfer function applied

(1)

25 1000 fs RMS

GEN4

PCIe Gen 4 Common Clock PCIe Gen 4 transfer function applied

(1)

25 500 fs RMS

(1) Refer to Parameter Measurement Information for relevant test conditions.

8.28 Typical Power Supply Noise Rejection Characteristics

(1)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG = 3.3 V, VDDO_x = 3.3 V, T

= 25°C, Reference Input = 50 MHz, PFD = 100

MHz, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Post Divider = 8, Output Divider = 4, AC-LVPECL/AC-LVDS/CML

output pair AC-coupled to 100-Ω differential load, HCSL outputs with 50 Ω || 2 pF to GND, sinusoidal noise injected in either

of the following supply nodes: VDD_IN, VDD_PLL, VDD_DIG or VDDO_x.

PARAMETER 50 mV RIPPLE ON SUPPLY TYPE UNIT

PSNR

50k

50-kHz spur on 156.25-MHz

output

–86 –87 –87 –110 –103 dBc

PSNR

100k

100-kHz spur on 156.25-

MHz output

–85 –86 –86 –110 –98 dBc

PSNR

500k

500-kHz spur on 156.25-

MHz output

–87 –89 –89 –110 –97 dBc

PSNR

1-MHz spur on 156.25-MHz

output

–91 –92 –92 –110 –94 dBc

(1) Refer to Parameter Measurement Information for relevant test conditions.

8.29 Typical Power Supply Noise Rejection Characteristics

(1)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG= 3.3 V, VDDO_x = 1.8 V, T

= 25°C, Reference Input = 50 MHz, PFD = 100

MHz, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Post Divider = 8, Output Divider = 4, AC-LVPECL/AC-LVDS/CML

output pair AC-coupled to 100-Ω differential load, HCSL outputs with 50 Ω || 2 pF to GND, sinusoidal noise injected in

VDDO_x.

PARAMETER 50 mV RIPPLE ON SUPPLY TYPE UNIT

PSNR

50k

50-kHz spur on 156.25-MHz

output

n/a n/a n/a n/a –93 dBc

PSNR

100k

100-kHz spur on 156.25-

MHz output

n/a n/a n/a n/a –88 dBc

PSNR

500k

500-kHz spur on 156.25-

MHz output

n/a n/a n/a n/a –78 dBc

PSNR

1-MHz spur on 156.25-MHz

output

n/a n/a n/a n/a –74 dBc

LMK03328

ZHCSE36D –AUGUST 2015–REVISED APRIL 2018

www.ti.com.cn

(1) Refer to Parameter Measurement Information for relevant test conditions.

8.30 Typical Closed-Loop Output Spur Characteristics

(1)

VDD_IN / VDD_PLL1 / VDD_PLL2 / VDD_DIG= 3.3V, VDDO_x = 1.8 V, 2.5 V, 3.3 V, T

= –40°C to 85°C, 50-MHz reference

input, 156.25-MHz or 125-MHz output with VCO Frequency = 5 GHz, Integer-N PLL, PLL Bandwidth = 400 kHz, Post Divider

= 8, Output Divider = 4 or 5, 161.1328125-MHz output with VCO Frequency = 5.15625 GHz, Fractional-N PLL, PLL

Bandwidth = 400 kHz, Post Divider = 8, Output Divider = 4, LVCMOS output load of 2 pF to GND, AC-LVPECL/AC-LVDS/AC-

CML output pair AC-coupled to 100-Ω differential load, HCSL outputs with 50 Ω || 2 pF to GND

PARAMETER CONDITION OUTPUT TYPE UNIT

SPUR-PFD

PFD/Reference Clock

Spurs

156.25 ± 78.125 MHz –77 –74 –76 –73 –75 dBc

SPUR-PFD

PFD/Reference Clock

Spurs

161.1328125 ±

80.56640625 MHz

–80 –77 –79 –77 –82 dBc

SPUR-

FRAC

Largest Fractional PLL

Spurs

161.1328125 ±

80.56640625 MHz

–74 –73 –76 –73 –74 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (PLL1

operational)

VICTIM

= 156.25 MHz

OUT4, f

AGGR

= 125

MHz OUT5, AC-

LVPECL aggressor

–73 –70 –70 –67 –74 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (PLL1

operational)

VICTIM

= 156.25 MHz

OUT4, f

AGGR

= 125

MHz OUT5, AC-LVDS

aggressor

–76 –74 –75 –71 –79 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (PLL1

operational)

VICTIM

= 156.25 MHz

OUT4, f

AGGR

= 125

MHz OUT5, HCSL

aggressor

–78 –74 –75 –72 –77 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (PLL1

operational)

VICTIM

= 156.25 MHz

OUT4, f

AGGR

= 125

MHz OUT5, LVCMOS

aggressor

–72 –70 –71 –66 –73 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (Both

PLLs operational)

VICTIM

= 161.1328125

MHz OUT4, f

AGGR

156.25 MHz OUT5, AC-

LVPECL aggressor

–69 –65 –67 –63 –73 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (Both

PLLs operational)

VICTIM

= 161.1328125

MHz OUT4, f

AGGR

156.25 MHz OUT5, AC-

LVDS aggressor

–73 –71 –72 –69 –82 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (Both

PLLs operational)

VICTIM

= 161.1328125

MHz OUT4, f

AGGR

156.25 MHz OUT5,

HCSL aggressor

–79 –75 –76 –69 –75 dBc

SPUR-OUT

Output Channel-to-

channel Isolation (Both

PLLs operational)

VICTIM

= 161.1328125

MHz OUT4, f

AGGR

156.25 MHz OUT5,

LVCMOS aggressor

–71 –69 –69 65 –74 dBc

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