LPC18XX微控制器用户手册

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"LPC18XX用户说明文档是针对基于ARMCortex-M3微控制器的LPC18XX系列的编程开发指南。该文档详细介绍了LPC1850、LPC1830、LPC1820、LPC1810及其衍生型号的特性与功能。涵盖了SPIFI、状态配置定时器（SCT）、USB、以太网等接口技术。" 在LPC18XX系列微控制器中，用户可以利用丰富的外设接口进行各种应用的开发。例如，SPIFI（SPI闪存接口）提供高速数据传输能力，适用于扩展存储需求；SCT是一种灵活的状态机，能够执行复杂的时序控制任务，适用于实时系统和电机控制；内置的USB控制器支持设备和主机模式，方便实现USB设备的设计；而集成的以太网控制器则使得LPC18XX系列具备了网络通信的能力。文档中提到了C_CANCLKDIV寄存器的描述修正和时钟分频值更新，这对于精确控制CAN总线的时钟频率至关重要，因为CAN通信的可靠性和速度都依赖于正确的时钟设置。此外，还增加了EMCSDRAM端口的优先级信息，这对于优化内存访问性能和确保系统稳定性很有帮助。关于OTP（一次性可编程）功能位置的更新，可能涉及了微控制器内部的一些固定配置选项或安全特性，这些选项在芯片出厂后只能编程一次。CANPCLK条件的增加指出，当CAN模块的时钟频率低于50MHz时，系统才能正常工作，这是设计CAN通信电路时必须考虑的硬件限制。在USB部分，对于自供电的USB0，文档强调了VBUS连接的需求，确保设备能够正确识别电源状态，这是USB设备合规性的重要部分。最后，RTC（实时时钟）的注册读取程序更新，特别是关于唤醒后的RTC报警寄存器读取，对于节能应用和精确时间管理非常关键。 LPC18XX用户手册提供了全面的技术指导，涵盖了硬件配置、外设操作、系统优化等多个方面，是开发者进行基于LPC18XX系列的项目开发时不可或缺的参考资料。

User manual Rev. 2.5 — 27 January 2014 16 of 1264

2.1 How to read this chapter

The following peripherals and memory blocks are only available on selected parts and are

reserved otherwise:

• Ethernet: available only on LPC185x/3x.

• USB0: available only on LPC185x/3x/2x.

• USB1: available only on LPC185x/3x.

• LCD: available only on parts LPC185x.

• SRAM: see Table 5.

• Flash: see Table 6.

2.2 Basic configuration

In the CREG block (see Table 93), select the interface to access the 16 kB block of RAM

located at address 0x2000 C000. This RAM memory block can be accessed either by the

Embedded Trace Buffer (ETB), or it can be used as normal SRAM on the AHB bus.

Remark: When the ETB is used, the 16 kB memory space at 0x2000 C000 must not be

used by any other process.

2.3 Memory configuration

2.3.1 On-chip static RAM

The LPC18xx support up to 136 kB SRAM (parts with on-chip flash) or up to 200 kB

SRAM (flashless parts LPC1850/30/20/10) with separate bus master access for higher

throughput and individual power control for low power operation (see Figure 7

and

Figure 8

When the Embedded Trace Buffer is used (see ETBCFG register, Table 93

), the 16 kB

memory space at 0x2000 C000 must not be used by any other process.

UM10430

Chapter 2: LPC18xx Memory mapping

Rev. 2.5 — 27 January 2014 User manual

User manual Rev. 2.5 — 27 January 2014 17 of 1264

NXP Semiconductors

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Chapter 2: LPC18xx Memory mapping

[1] Top 8 kB at 0x1008 8000 remain powered on in Sleep, Deep-sleep, and Power-down modes (see

Tab le 98

[2] To configure SRAM for AHB or ETB access, see Table 93

2.3.2 Bit banding

Bit-banding offers efficient bit accesses. Bits in the bit-band region (0x2000 0000 to

0x2010 0000 and 0x4000 0000 to 0x40100000) can be accessed in the so-called alias

region at 0x2200 0000 and 0x4200 0000. Reads return the respective bit from the

bit-band region. Writes perform an atomic read-modify-write on the respective bit of the

bit-band region. For details, see the ARM Cortex-M3 technical reference manual.

Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see

Section 25.6.10

Remark: Although the EEPROM is mapped in a bit-banding capable region, attempts to

write access the EEPROM in the bit-banding aliased memory space will not result in a bit

write

2.3.3 On-chip flash

The available flash configuration for the LPC185x/3x/2x/1x is shown in Table 6. An

integrated flash accelerator maximizes performance for use with the two fast AHB buses.

Table 5. LPC18xx SRAM configuration

Part Local SRAM Local SRAM

[1]

AHB

SRAM

AHB

SRAM

AHB

SRAM

/ETB

SRAM

[2]

0x1000 0000

0x1008 0000

0x2000 0000

0x2000 8000

0x2000 C000

LPC1850 96 kB 40 kB 32 kB 16 kB 16 kB Figure 3

LPC1830 96 kB 40 kB 32 kB 16 kB 16 kB Figure 3

LPC1820 96 kB 40 kB 16 kB - 16 kB Figure 3

LPC1810 64 kB 40 kB 16 kB - 16 kB Figure 3

LPC185x 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC183x 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC1827 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC1825 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC1823 32 kB 40 kB 16 kB - 16 kB Figure 5

LPC1822 32 kB 40 kB 16 kB - 16 kB Figure 5

LPC1817 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC1815 32 kB 40 kB 32 kB 16 kB 16 kB Figure 5

LPC1813 32 kB 40 kB 16 kB - 16 kB Figure 5

LPC1812 32 kB 40 kB 16 kB - 16 kB Figure 5

User manual Rev. 2.5 — 27 January 2014 18 of 1264

NXP Semiconductors

UM10430

Chapter 2: LPC18xx Memory mapping

The flash memory interface includes an intelligent buffering scheme. It can be beneficial

to locate code and static data over the two flash memories to enable parallel code and

data access or to avoid that interrupts corrupt buffer content. The buffers are aligned on

32-byte boundaries.

2.3.4 On-chip EEPROM

The LPC185x/3x parts with flash also include a 16 kB EEPROM. The EEPROM is divided

into 128 pages. The last EEPROM page is protected.

2.3.5 Memory retention in the Power-down modes

In Deep-sleep mode, all SRAM content is retained. At wake-up the system can restart

immediately.

In Power-down mode, only the top 8 kB of SRAM block starting at 0x1008 0000 is retained

- that is the upper 8 kB of the SRAM block starting at 0x1008 8000. All other SRAM

content is lost. Common practice is to store the stack and other variables that need to be

retained in this 8 kB memory space as well as code to restart the rest of the system.

In Deep power-down mode, no SRAM content is retained. Variables that need to be

retained in deep power down can be stored in the 256-byte register file located in the RTC

domain at 0x4004 1000.

2.3.6 Memory Protection Unit (MPU)

The MPU is a integral part of the ARM Cortex-M3 for memory protection and supported by

all LPC18xx parts. The processor supports the standard ARMv7 Protected Memory

System Architecture model. The MPU provides full support for:

• protection regions

• overlapping protection regions, with ascending region priority (7 = highest priority, 0 =

lowest priority)

• access permissions

• exporting memory attributes to the system

MPU mismatches and permission violations invoke the programmable-priority

MemManage fault handler. See the ARMv7-M Architecture Reference Manual for more

information.

Table 6. LPC185x/3x/2x/1x Flash configuration

Part Flash bank A

256 kB

Flash bank A

128 kB

Flash bank A

128 kB

Flash bank B

256 kB

Flash bank B

128 kB

Flash bank B

128 kB

Total flash

0x1A00 0000 0x1A04 000 0x1A0 6000 0x1B00 0000 0x1B04 000 0x1B0 6000

LPC18x7 yes yes yes yes yes yes 1 MB

LPC18x5 yes yes no yes yes no 768 kB

LPC18x3 yes no no yes no no 512 kB

LPC18x2 yes yes yes no no no 512 kB

User manual Rev. 2.5 — 27 January 2014 20 of 1264

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Chapter 2: LPC18xx Memory mapping

2.4 Memory map (flashless parts LPC1850/30/20/10)

Fig 3. System memory map - flashless parts LPC1850/30/20/10 (see Figure 4 for detailed addresses of all

peripherals)

reserved

peripheral bit band alias region

reserved

high-speed GPIO

reserved

0x0000 0000

0 GB

1 GB

4 GB

0x2001 0000

0x2200 0000

0x2400 0000

0x2800 0000

0x1000 0000

0x3000 0000

0x4000 0000

0x4001 2000

0x4004 0000

0x4005 0000

0x4010 0000

0x4400 0000

0x6000 0000

AHB peripherals

APB peripherals #0

APB peripherals #1

reserved

RTC domain peripherals

0x4006 0000

0x4008 0000

0x4009 0000

0x400A 0000

0x400B 0000

0x400C 0000

0x400D 0000

0x400E 0000

0x400F 0000

0x400F 1000

0x400F 2000

0x400F 4000

0x400F 8000

clocking/reset peripherals

APB peripherals #2

APB peripherals #3

0x2000 8000

16 kB AHB SRAM (LPC1850/30)

16 kB AHB SRAM (LPC1850/30/20/10)

0x2000 C000

16 kB AHB SRAM (LPC1850/30)

16 kB AHB SRAM (LPC1850/30/20/10)

reserved

0x4010 1000

0x4010 2000

0x4200 0000

reserved

local SRAM/

external static memory banks

0x2000 0000

0x2000 4000

128 MB dynamic external memory DYCS0

256 MB dynamic external memory DYCS1

256 MB dynamic external memory DYCS2

256 MB dynamic external memory DYCS3

0x7000 0000

0x8000 0000

0x8800 0000

0xE000 0000

256 MB shadow area

LPC1850/30/20/10

0x1000 0000

0x1001 8000

0x1008 0000

0x1008 A000

0x1040 0000

0x1041 0000

0x1C00 0000

0x1D00 0000

reserved

32 MB AHB SRAM bit banding

reserved

0xE010 0000

0xFFFF FFFF

reserved

SPIFI data

ARM private bus

reserved

0x1001 0000

32 kB local SRAM (LPC1850/30/20)

64 kB local SRAM

(LPC1850/30/20/10)

32 kB + 8 kB local SRAM

(LPC1850/30/20/10)

reserved

64 kB ROM

0x1E00 0000

0x1F00 0000

0x2000 0000

16 MB static external memory CS3

16 MB static external memory CS2

16 MB static external memory CS1

16 MB static external memory CS0

0x1400 0000

0x1800 0000

64 MB SPIFI data

002aaf228

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