STM32L431RCT6超低功耗ARM Cortex-M4微控制器数据手册

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"STM32L431RCT6是一款基于ARM Cortex-M4内核的超低功耗微控制器，由意法半导体（STMicroelectronics）生产，适用于各种需要高效能和节能的应用。该器件拥有丰富的内存配置、高级模拟功能以及音频支持。STM32L431RCT6的数据手册详细介绍了其各项特性和技术规格，包括电源管理、处理器性能、低功耗模式、唤醒速度、时钟源和安全特性等。" STM32L431RCT6是STM32系列的一款超低功耗微控制器，设计用于在广泛的电压范围内（1.71V到3.6V）工作，并且能够适应广泛的温度范围（-40°C至85/105/125°C）。其突出的低功耗特性包括： 1. VBAT模式下，仅消耗200nA的电流，可以为RTC（实时计时器）和32x32-bit备份寄存器供电。 2. 关机模式下，5个唤醒引脚的电流仅为8nA。 3. 站立模式下，同样有5个唤醒引脚，电流为28nA；若带有RTC，则增加到280nA。 4. Stop2模式下，电流分别为1.0µA（不带RTC）和1.28µA（带RTC）。 5. 运行模式下，以84µA/MHz的电流运行。 6. 提供快速唤醒功能，从Stop模式下4µs内唤醒。 7. 包含BOR（Brownout Reset）功能，除关机模式外的所有模式都具备。 STM32L431RCT6的核心是高性能的ARM Cortex-M4处理器，带有浮点单元（FPU），可实现高达100DMIPS的运算速度。它还集成了Adaptive Real-Time Accelerator（ART Accelerator），允许在Flash内存中零等待状态执行，最高频率可达80MHz。此外，它还配备了内存保护单元（MPU），根据Dhrystone 2.1基准测试，每MHz性能为1.25DMIPS。在能效方面，STM32L431RCT6具有出色的性能，ULPBench®分数达到176.7分，表明其在低功耗应用中的高效表现。时钟源方面，该芯片支持多种选项，从4MHz到最高频率，包括内部RC振荡器、外部晶体或陶瓷谐振器，以及HSE（高速外部时钟）、LSE（低速外部时钟）等。这些时钟源提供了灵活性，可以根据应用需求进行选择和配置。此外，STM32L431RCT6还具备Interconnect Matrix，增强了系统内部的通信能力。同时，它提供了批量采集模式（BAM）以优化传感器数据读取时的功耗。其他安全特性如Brownout Reset确保了系统在电源电压下降时的稳定性。 STM32L431RCT6是针对能源效率和高性能应用的理想选择，适用于需要长时间电池寿命和复杂处理任务的物联网(IoT)设备、穿戴设备、医疗设备、工业控制等领域。

Functional overview STM32L431xx

16/200 DocID028800 Rev 1

3 Functional overview

3.1 ARM

Cortex

-M4 core with FPU

The ARM

Cortex

-M4 with FPU processor is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The ARM

Cortex

-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an ARM core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded ARM core, the STM32L431xx family is compatible with all ARM tools

and software.

Figure 1 shows the general block diagram of the STM32L431xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM

Cortex

-M4 processors. It balances the inherent performance advantage of

the ARM

Cortex

-M4 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DocID028800 Rev 1 17/200

STM32L431xx Functional overview

3.4 Embedded Flash memory

STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for

storing programs and data in single bank architecture. The Flash memory contains 128

pages of 2 Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)

allows to select if the PCROP area is erased or not when the RDP protection is

changed from Level 1 to Level 0.

Table 3. Access status versus readout protection level and execution modes

Area

Protection

level

User execution

Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

Main

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased when RDP change from Level 1 to Level 0.

No No N/A

(1)

2 Yes Yes N/A N/A N/A N/A

SRAM2

1 Yes Yes Yes

(1)

No No No

(1)

2 Yes Yes Yes N/A N/A N/A

Functional overview STM32L431xx

18/200 DocID028800 Rev 1

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two

blocks:

• 48 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2000 C000, offering a contiguous address

space with the SRAM1 (16 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.

These 16 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:

– code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

DocID028800 Rev 1 19/200

STM32L431xx Functional overview

3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select

one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the

value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the

first flash memory location is not programmed and if the boot selection is configured to boot

from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART, I2C, SPI and CAN in Device mode through DFU (device firmware upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• V

= 1.71 to 3.6 V: external power supply for I/Os (V

DDIO1

), the internal regulator and

the system analog such as reset, power management and internal clocks. It is provided

externally through V

pins.

• V

DDA

= 1.62 V (ADCs/COMPs) / 1.8 (DACs/OPAMP) to 3.6 V: external analog power

supply for ADCs, DACs, OPAMP, Comparators and Voltage reference buffer. The V

DDA

voltage level is independent from the V

voltage.

• V

BAT

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

Note: When the functions supplied by V

DDA

are not used, this supply should preferably be shorted

to V

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Table 18: Voltage characteristics).

Note: V

DDIOx

is the I/Os general purpose digital functions supply. V

DDIOx

represents V

DDIO1

, with

DDIO1

= V

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