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Nexys4™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
2.3 USB Host and Micro SD Programming
You can program the FPGA from a pen drive attached to the USB-HID port (J5) or a microSD card inserted into J1 by
doing the following:
1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the Nexys4.
4. Set the JP1 Programming Mode jumper on the Nexys4 to “USB/SD”.
5. Select the desired storage device using JP2.
6. Push the PROG button or power-cycle the Nexys4.
The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not
built for the proper Artix-7 device will be rejected by the FPGA.
The Auxiliary Function Status or “BUSY” LED gives visual feedback on the state of the configuration process when
the FPGA is not yet programmed:
When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration
medium (microSD or pen drive) and downloading a bitstream to the FPGA.
A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
In case of an error during configuration the LED will blink rapidly.
When the FPGA is has been successfully configured, the behavior of the LED is application-specific. For example, if
a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.
3 Memory
The Nexys4 board contains two external memories: a 128Mbit Cellular RAM (pseudo-static DRAM) and a 128Mbit
non-volatile serial Flash device. The Cellular RAM has an SRAM interface, and the serial Flash is on a dedicated
quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are
shown in Figure 4 and Table 3.
The 16Mbyte Cellular RAM (Micron part number M45W8MW16) has a 16-bit bus that supports 8 or 16 bit data
access. It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns, or as a synchronous
memory with a 104MHz bus. When operated as an asynchronous SRAM, the Cellular RAM automatically refreshes
its internal DRAM arrays, allowing for a simplified memory controller (similar to any SRAM controller). When
operated in synchronous mode, continuous transfers of up to 104MHz are possible.
FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL128S), and mode
settings are available to cause the FPGA to automatically read a configuration from this device at power on. An
Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device
available for user data.
NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more
information about the memory devices.